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參數(shù)資料
| 型號： | MPC603AFE66AC |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.67 MHz, RISC PROCESSOR, CQFP240 |
| 封裝： | 32 X 32 MM, 3.10 MM HEIGHT, 0.50 MM PITCH, WIRE BOND, CERAMIC, QFP-240 |
| 文件頁數(shù)： | 14/31頁 |
| 文件大?。?/td> | 153K |
| 代理商： | MPC603AFE66AC |
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603 Hardware Specifications
21
1.8 System Design Information
This section provides electrical and thermal design recommendations for successful application of the 603.
1.8.1 PLL Conguration
The 603 PLL is congured by the PLL_CFG[0–3] signals. For a given SYSCLK (bus) frequency, the PLL
conguration signals set the internal CPU and VCO frequency of operation. The PLL conguration for the
603 is shown in Table 11 for nominal frequencies.
Table 11. PowerPC 603 Microprocessor PLL Configuration
PLL_CFG[0–3]
CPU Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to-
VCO
Multiplier
Bus
16.6 MHz
Bus
20 MHz
Bus
25 MHz
Bus
33.3 MHz
Bus
40 MHz
Bus
50 MHz
Bus
66.6 MHz
0000
1x
2x
—
66.6
(133)
0001
1x
4x
—
33.3
(133)
40
(160)
50
(200)
—
0010
1x
8x
16.6
(133)
20
(160)
25
(200)
—
———
0100
2x
—
66.6
(133)
80
(160)
——
0101
2x
4x
33.3
(133)
40
(160)
50
(200)
—
———
1000
3x
2x
—
60
(120)
75
(150)
—
———
1001
3x
4x
50
(200)
60
(240)
——
———
1100
4x
2x
66.6
(133)
80
(160)
——
———
0011
PLL bypass
1111
Clock off
Notes:
1. The sample bus-to-core frequencies shown are for reference only.
2. Some PLL congurations may select bus, CPU, or PLL frequencies which are not supported by the 603; see
Section 1.4.2.2, “Input AC Specications,” for valid SYSCLK frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus
mode is set for 1:1 mode operation. This mode is intended for factory use only. Note: The AC timing specications
given in this document do not apply in PLL-bypass mode.
4. In clock-off mode, no clocking occurs inside the 603 regardless of the SYSCLK input.
5. PLL_CFG[0–1] signals select the CPU-to-bus ratio (1:1, 2:1, 3:1, 4:1), PLL_CFG[2–3] signals select the CPU-to-PLL
multiplier (x2, x4, x8).
AR
CH
IVE
D B
Y F
RE
ES
CA
LE
SE
MI
CO
ND
UC
TO
R,
INC
.
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