MOTOROLA
Chapter 10. Memory Controller
10-39
Programming Model
21:22
ACS
Address to chip-select setup. Following a system reset, the ACS bits are reset in OR[0].
00 CS is asserted at the same time that the address lines are valid.
01 Reserved
10 CS is asserted a quarter of a clock after the address lines are valid.
11 CS is asserted half a clock after the address lines are valid
Following a system reset, the ACS bits are cleared in OR[0].
23
EHTR
Extended hold time on read accesses. This bit, when asserted, inserts an idle clock cycle after a
read access from the current bank and any MPC565/MPC566 write accesses or read accesses
to a different bank.
0 Memory controller generates normal timing
1 Memory controller generates extended hold timing
Following a system reset, the EHTR bits are cleared in OR[0].
24:27
SCY
Cycle length in clocks. This four-bit value represents the number of wait states inserted in the
single cycle, or in the first beat of a burst, when the GPCM handles the external memory access.
Values range from 0 (0b0000) to 15 (0b1111). This is the main parameter for determining the
length of the cycle.
The total cycle length may vary depending on the settings of other timing attributes.
The total memory access length is (2 + SCY) x Clocks.
If an external TA response is selected for this memory bank (by setting the SETA bit), then the
SCY field is not used.
Following a system reset, the SCY bits are set to 0b1111 in OR[0].
28:30
BSCY
Burst beats length in clocks. This field determines the number of wait states inserted in all burst
beats except the first, when the GPCM starts handling the external memory access and thus
using SCY[0:3] as the main parameter for determining the length of that cycle.
The total cycle length may vary depending on the settings of other timing attributes.
The total memory access length for the beat is (1 + BSCY) x Clocks.
If an external TA response has been selected for this memory bank (by setting the SETA bit) then
BSCY[0:3] are not used.
000 0-clock-cycle (1 clock per data beat)
001 1-clock-cycle wait states (2 clocks per data beat)
010 2-clock-cycle wait states (3 clocks per data beat)
011 3-clock-cycle wait states (4 clocks per data beat)
1xx Reserved
Following a system reset, the BSCY bits are set to 0b011 in OR[0].
31
TRLX
Timing relaxed. This bit, when set, modifies the timing of the signals that control the memory
devices during a memory access to this memory region. Relaxed timing multiplies by two the
number of wait states determined by the SCY and BSCY fields. Refer to
Section 10.3.5,0 Normal timing is generated by the GPCM.
1 Relaxed timing is generated by the GPCM
Following a system reset, the TRLX bit is set in OR[0].
Table 10-10. OR[0] – OR[3] Bit Descriptions (continued)
Bit(s)
Name
Description