9-18
MPC565/MPC566 Reference Manual
MOTOROLA
Bus Operations
(USIU)” for further details. The MPC565/MPC566 begins the access by supplying a
starting address that points to one of the words in the array and requires the memory to
sequentially drive or sample each word on the data bus. The selected slave device must
internally increment ADDR[28] and ADDR[29] (and ADDR[30]in the case of a 16-bit port
slave device, and also ADDR[31] in the case of an 8-bit port slave device) of the supplied
address for each transfer, causing the address to reach a four/eight word boundary, and then
stop. The address and transfer attributes supplied by the MPC565/MPC566 remain stable
during the transfers. The selected device terminates each transfer by driving or sampling
the word on the data bus and asserting TA.
The MPC565/MPC566 also supports burst-inhibited transfers for slave devices that are
unable to support bursting. For this type of bus cycle, the selected slave device supplies or
samples the first word the MPC565/MPC566 points to and asserts the burst-inhibit signal
with TA for the first transfer of the burst access. The MPC565/MPC566 responds by
terminating the burst and accessing the remainder of the 16-byte block. These remaining
accesses use up to three read/write bus cycles (each one for a word) in the case of a 32-bit
port width slave, up to seven read/write bus cycles in the case of a 16-bit port width slave,
or up to fifteen read/write bus cycles in the case of a 8-bit port width slave.
The general case of burst transfers assumes that the external memory has a 32-bit port size.
The MPC565/MPC566 provides an effective mechanism for interfacing with 16-bit and
8-bit port size memories, allowing bursts transfers to these devices when they are controlled
by the internal memory controller.
In this case, the MPC565/MPC566 attempts to initiate a burst transfer as in the normal case.
If the memory controller signals to the bus interface that the external device has a small port
size (8 or 16 bits), and if the burst is accepted, the bus interface completes a burst of 16 or
8 beats respectively for four words. Eight words requires 32 or 16 beats. Each beat of the
burst transfers only one or two bytes effectively. Note that this burst of 8 or 16 beats is
considered an atomic transaction, so the MPC565/MPC566 does not allow other unrelated
master accesses or bus arbitration to intervene between the transfers.
9.5.5
Burst Mechanism
In addition to the standard bus signals, the MPC565/MPC566 burst mechanism uses the
following signals:
The BURST signal indicates that the cycle is a burst cycle.
The burst data in progress (BDIP) signal indicates the duration of the burst data.
The burst inhibit (BI) signal indicates whether the slave is burstable.
At the start of the burst transfer, the master drives the address, the address attributes, and
the BURST signal to indicate that a burst transfer is being initiated, and asserts TS.Ifthe