MOTOROLA
Chapter 8. Clocks and Power Control
8-33
Clocks Unit Programming Model
1:2
COM
Clock Output Mode – The COM and CQDS bits control the output buffer strength of the
CLKOUT and external bus pins. When both COM bits are set the CLKOUT pin is held in
the high (1) state and external bus pins are driven at reduced drive. These bits can be
dynamically changed without generating spikes on the CLKOUT and external bus pins. If
CLKOUT pin is not connected to external circuits, set both bits (disabling CLKOUT) to
minimize noise and power dissipation. The default value for COM[1] is determined by the
BDRV bit in the reset configuration word. See
Table 7-5. For CLKOUT control see
3
DCSLR
Disable clock switching at loss of lock during reset. When DCSLR is clear and limp mode
is enabled, the chip will switch automatically to the backup clock if the PLL losses lock
during HRESET. When DCSLR is asserted, a PLL loss-of-lock event does not cause clock
switching. If HRESET is asserted and DCSLR is set, the chip will not negate HRESET until
the PLL acquires lock.
0 Enable clock switching if the PLL loses lock during reset
1 Disable clock switching if the PLL loses lock during reset
4
MFPDL
MF and pre-divider lock. Setting this control bit disables writes to the MF and DIVF bits. This
helps prevent runaway software from changing the VCO frequency and causing the SPLL
to lose lock. In addition, to protect against hardware interference, a hardware reset will be
asserted if these fields are changed while LPML is asserted. This bit is writable once after
power-on reset.
0 MF and DIVF fields are writable
1 MF and DIVF fields are locked
5
LPML
LPM lock. Setting this control bit disables writes to the LPM and CSRC control bits. In
addition, for added protection, a hardware reset is asserted if any mode is entered other
than normal-high mode. This protects against runaway software causing the MCU to enter
low-power modes. (The MSR[POW] bit provides additional protection). LPML is writable
once after power-on reset.)
0 LPM and CSRC bits are writable
1 LPM and CSRC bits are locked and hard reset will occur if the MCU is not in normal-high
mode
6
TBS
Time base source.
0 Source is OSCCLK divided by either 4 or 16
1 Source is system clock divided by 16
7
RTDIV
RTC (and PIT) clock divider. At power-on reset this bit is cleared if MODCK[1:3] are all low;
otherwise the bit is set.
0 RTC and PIT clock divided by 4
1 RTC and PIT clock divided by 256
8
STBUC
Switch to backup clock control. When software sets this bit, the system clock is switched to
the on-chip backup clock ring oscillator, and the chip undergoes a hard reset. The STBUC
bit is ignored if LME is cleared.
0 Do not switch to the backup clock ring oscillator
1 Switch to backup clock ring oscillator
9
CQDS
Clock quarter drive strength — The COM and CQDS bits control the output buffer strength
Table 8-9. SCCR Bit Descriptions (continued)
Bits
Name
Description