- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45338 > MPC5567MZQ112 (FREESCALE SEMICONDUCTOR INC) FLASH, 112 MHz, MICROCONTROLLER, PBGA324 PDF資料下載
參數(shù)資料
| 型號： | MPC5567MZQ112 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FLASH, 112 MHz, MICROCONTROLLER, PBGA324 |
| 封裝： | 23 X 23 MM, 1 MM PITCH, PLASTIC, MS-034AAJ-1, BGA-324 |
| 文件頁數(shù)： | 14/66頁 |
| 文件大?。?/td> | 1903K |
| 代理商： | MPC5567MZQ112 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
Electrical Characteristics
MPC5567 Microcontroller Data Sheet, Rev. 1.0
Freescale Semiconductor
21
19
CLKOUT period jitter, measured at fSYS max:
15, 16
Peak-to-peak jitter (clock edge to clock edge)
Long term jitter (averaged over a 2 ms interval)
CJITTER
—
5.0
0.01
%
fCLKOUT
20
Frequency modulation range limit 17
(do not exceed fsys maximum)
CMOD
0.8
2.4
%fSYS
21
ICO frequency
fico = [ fref_crystal × (MFD + 4) ] ÷ (PREDIV + 1)
18
fico = [ fref_ext × (MFD + 4) ] ÷ (PREDIV + 1)
fico
48
fMAX
MHz
22
Predivider output frequency (to PLL)
fPREDIV
42019
MHz
1 Nominal crystal and external reference values are worst-case not more than 1%. The device operates correctly if the frequency
remains within ± 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time.
The designer must thoroughly understand the drift margin of the source clock.
2 The 8–20 MHz crystal or external reference values have PLLCFG[2] pulled low.
3 The 20–40 MHz crystal and external reference values have PLLCFG[2] pulled high, and the minimum frequency must be greater
than 20 MHz. Use the 8–20 MHz setting (PLLCFG[2] pulled low) if a 20 MHz crystal or external reference is required.
To exit RESET when using 40 MHz, set PLLCFG[2] to 1.
4 All internal registers retain data at 0 Hz.
5 Up to the maximum frequency rating of the device (refer to Table 1).
6 Loss of reference frequency is defined as the reference frequency detected internally, which transitions the PLL into self-clocked
mode.
7 The PLL operates at self-clocked mode (SCM) frequency when the reference frequency falls below f
LOR. SCM frequency is
measured on the CLKOUT ball with the divider set to divide-by-two of the system clock.
NOTE: In SCM, the MFD and PREDIV have no effect and the RFD is bypassed.
8 Use the EXTAL input high voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (Vextal – Vxtal) must be ≥ 400 mV for the oscillator’s comparator to produce the output clock.
9 Use the EXTAL input low voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (Vxtal –Vextal) must be ≥ 400 mV for the oscillator’s comparator to produce the output clock.
10 I
xtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
11 C
PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
12 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time also includes the crystal
startup time.
13 PLL is operating in 1:1 PLL mode.
14 V
DDE = 3.0–3.6 V.
15 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
sys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage
for a given interval. CLKOUT divider is set to divide-by-two.
16 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of (jitter + Cmod).
17 Modulation depth selected must not result in f
sys value greater than the fsys maximum specified value.
18 f
sys = fico ÷ (2
RFD)
19 Maximum value for dual controller (1:1) mode is (f
MAX ÷ 2) with the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).
Table 12. FMPLL Electrical Specifications (continued)
(VDDSYN = 3.0–3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH)
Spec
Characteristic
Symbol
Minimum
Maximum
Unit
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MPC551x
and
MPC5533
products
in
208
MAPBGA
packages;
MPC5534
and
MPC5553
products
in
208
and
496
MAPBGA
packages;
MPC5554,
MPC5565,
MPC5566
and
MPC5567
products
in
496
MAPBGA
packages
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC5567MVZ80 | FLASH, 80 MHz, MICROCONTROLLER, PBGA324 |
| MPC5567MVR112 | FLASH, 112 MHz, MICROCONTROLLER, PBGA416 |
| MPC5601PEF0VLL6 | 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP100 |
| MPC5602F0VLH6R | 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP64 |
| MPC5602PEF0MLH6R | 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC5567MZQ112R2 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller |
| MPC5567MZQ132 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller |
| MPC5567MZQ132R2 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller |
| MPC5567MZQ80 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller |
| MPC5567MZQ80R2 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。