Table 16 FLASH BIU Settings vs. F" />
參數(shù)資料
型號： MPC5567EVBE
廠商： Freescale Semiconductor
文件頁數(shù)： 61/68頁
文件大小： 0K
描述： BOARD EVALUATION MPC5567
標(biāo)準(zhǔn)包裝： 1
類型： MCU
適用于相關(guān)產(chǎn)品： MPC5567MZP132
所含物品： 板，線纜，CD，ICD，電源
MPC5567 Microcontroller Data Sheet, Rev. 2
Revision History for the MPC5567 Data Sheet
Freescale Semiconductor
64
Table 16 FLASH BIU Settings vs. Frequency of Operations:
‘Added footnote 1 to the end of the table title, The footnote reads: ‘Illegal combinations exist. Use entries from
the same row in this table.’
Moved footnote 2:’ For maximum flash performance, set to 0b11’ to the ‘DPFEN’ column header.
Deleted the x-refs in the ‘DPFEN’ column for the rows.
Created a x-ref for footnote 2 and inserted in the ‘IPFEN’ column header.
Deleted the x-refs in the ‘IPFEN’ column for the rows.
Moved footnote 3:’ For maximum flash performance, set to 0b110’ to the ‘PFLIM’ column header.
Deleted the x-refs in the ‘PFLIM’ column for the rows.
Moved footnote 4:’ For maximum flash performance, set to 0b1’ to the ‘BFEN’ column header.
Deleted the x-refs in the ‘BFEN’ column for the rows.
Changed footnotes 1, 5, and 6 to become footnotes 5, 6, and 7
-- footnote 5 82 MHz parts allow for 80 MHz system clock + 2% frequency modulation (FM).
-- footnote 6 102 MHz parts allow for 100 MHz system clock + 2% FM.
-- footnote 7 135 MHz parts allow for 132 MHz system clock + 2% FM.
Footnote 9: added to the end of the 1st column for the 147 MHz row that reads:
Preliminary setting. Final setting pending characterization.
Table 17 Pad AC Specifications and Table 18 Derated Pad AC Specifications: The changes are identical in the tables.
Footnote 1, deleted ‘FSYS = 132 MHz.’
Footnote 2, changed from ‘tested’ to ‘(not tested).’
Footnote 3, changed from ‘Out delay. . .’ to ‘The output delay. . .’,
Changed from ‘ Add a maximum of one system clock to the output delay to get the output delay with respect to
the system clock‘ to ‘To calculate the output delay with respect to the system clock, add a maximum of one
system clock to the output delay.’
Footnote 4: changed ‘Delay’ to ‘The output delay.’
Footnote 5: deleted ‘before qualification.’
Changed from ‘This parameter is supplied for reference and is not guaranteed by design and not tested’ to ‘This
parameter is supplied for reference and is guaranteed by design and tested.’
Table 19 Reset and Configuration Pin Timing: Footnote 1, deleted ‘FSYS = 132 MHz,’ and ‘VDD = 1.35–1.65.’
Table 20 JTAG Pin AC Electrical Characteristics:
Footnote 1, deleted: ‘, and CL = 30 pF with DSC = 0b10, SRC = 0b11’
Footnote 1, changed ‘functional’ to ‘Nexus.’
Table 21 Nexus Debug Port Timing.
Changed Spec 12, TCK Low to TDO Data Valid: Changed ‘VDDE = 3.0 to 3.6 volts’ maximum value in column 4
from 9 to 10. Now reads ‘VDDE = 3.0–3.6 V’ with a max value of 10.
Table 35. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued)
Location
Description of Changes
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC5567MVR112 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller
MPC5567MVR112R2 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller
MPC5567MVR132 制造商:Freescale Semiconductor 功能描述: 制造商:Freescale Semiconductor 功能描述:2MB FLASH W/ECC, 5 CANS - Trays
MPC5567MVR132R2 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller
MPC5567MVR80 制造商:Freescale Semiconductor 功能描述:2MB FLASH W/ECC, 5 CANS - Trays
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