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| 型號(hào)： | MPC5200CVR400B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 400 MHz, MICROPROCESSOR, PBGA272 |
| 封裝： | 27 X 27 MM, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-272 |
| 文件頁(yè)數(shù)： | 44/78頁(yè) |
| 文件大小： | 1100K |
| 代理商： | MPC5200CVR400B |
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Electrical and Thermal Characteristics
MPC5200B Data Sheet, Rev. 1
Freescale Semiconductor
49
3.3.13 I2C
NOTE
Output timing is specified at a nominal 50 pF load.
Table 40. I2C Input Timing Specifications—SCL and SDA
Sym
Description
Min
Max
Units
SpecID
1
Start condition hold time
2
—
IP-Bus Cycle(1)
NOTES:
1
Inter Peripheral Clock is defined in the MPC5200B User Manual [1].
A13.1
2
Clock low time
8
—
IP-Bus Cycle(1)
A13.2
4
Data hold time
0.0
—
ns
A13.3
6
Clock high time
4
—
IP-Bus Cycle(1)
A13.4
7
Data setup time
0.0
—
ns
A13.5
8
Start condition setup time (for repeated start condition
only)
2
—
IP-Bus Cycle(1)
A13.6
9
Stop condition setup time
2
—
IP-Bus Cycle(1)
A13.7
Table 41. I2C Output Timing Specifications—SCL and SDA
Sym
Description
Min
Max
Units
SpecID
1(1)
NOTES:
1
Programming IFDR with the maximum frequency (IFDR=0x20) results in the minimum output timings listed. The
I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed in IFDR.
Start condition hold time
6
—
IP-Bus Cycle(3)
A13.8
2(1)
Clock low time
10
—
IP-Bus Cycle(3)
A13.9
3(2)
2
Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL
or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values
SCL/SDA rise time
—
7.9
ns
A13.10
4(1)
Data hold time
7
—
IP-Bus Cycle(3) A13.11
5(1)
SCL/SDA fall time
—
7.9
ns
A13.12
6(1)
Clock high time
10
—
IP-Bus Cycle(3) A13.13
7(1)
Data setup time
2
—
IP-Bus Cycle(3) A13.14
8(1)
Start condition setup time (for repeated start condition
only)
20
—
IP-Bus Cycle(3) A13.15
9(1)
Stop condition setup time
10
—
IP-Bus Cycle(3)
3
Inter Peripheral Clock is defined in the MPC5200B User Manual [1].
A13.16
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC5200CVR400B | 制造商:Freescale Semiconductor 功能描述:IC, 32BIT PROCESSOR |
| MPC5200CVR400BR2 | 制造商:Freescale Semiconductor 功能描述:MPU MPC52XX RISC 32BIT 400MHZ 2.5V/3.3V 272BGA - Tape and Reel |
| MPC5200CVR466B | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SDRAM/DDR Memory Controller |
| MPC5200ID | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC5200 Hardware Specifications |
| MPC5200VR400 | 功能描述:微處理器 - MPU NO-PB COMM 5200 400MHZ RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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