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參數(shù)資料
| 型號： | MPC5200CBV266 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MPC5200 Hardware Specifications |
| 中文描述： | 266 MHz, RISC PROCESSOR, PBGA272 |
| 封裝： | 27 X 27 MM, 1.27 MM PITCH, PLASTIC, BGA-272 |
| 文件頁數(shù)： | 17/76頁 |
| 文件大?。?/td> | 1404K |
| 代理商： | MPC5200CBV266 |
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MOTOROLA
MPC5200 Hardware Specifications
17
Electrical and Thermal Characteristics
3.3.3 Resets
The MPC5200 has three reset pins:
PORESET - Power on Reset
HRESET - Hard Reset
SRESET - Software Reset
These signals are asynchronous I/O signals and can be asserted at any time. The input side uses a
Schmitt trigger and requires the same input characteristics as other MPC5200 inputs, as specified in the
DC Electrical Specifications section.
Table 14
specifies the pulse widths of the Reset inputs.
Notes:
1.
For PORESET the value of the minimum pulse width reflects the power on sequence. If PORESET is asserted after-
wards its minimum pulse width equals the minimum given for HRESET related to the same reference clock.
The t
VDD_stable
describes the time which is needed to get all power supplies stable.
For t
lock,
refer to the Oscillator/PLL section of this specification for further details.
For t
up_osc,
refer to the Oscillator/PLL section of this specification for further details.
Following the deassertion of PORESET, HRESET and SRESET remain low for 4096 reference clock cycles.
The deassertion of HRESET for at least the minimum pulse width forces the internal resets to be active for an additional
4096 clock cycles.
2.
3.
4.
5.
6.
NOTE:
As long as VDD is not stable the HRESET output is not stable.
For additional information, see the MPC5200 User Manual [1].
NOTE:
Make sure that the PORESET does not carry any glitches. The MPC5200
has no filter to prevent them from getting into the chip.
Table 14 Reset Pulse Width
Name
Description
Min Pulse Width
Max Pulse
Width
Reference Clock
SpecID
PORESET
Power On Reset t
VDD_stable
+t
up_osc
+t
lock
—
SYS_XTAL_IN
A3.1
HRESET
Hardware Reset
4 clock cycles
—
SYS_XTAL_IN
A3.2
SRESET
Software Reset
4 clock cycles
—
SYS_XTAL_IN
A3.3
Table 15 Reset Rise / Fall Timing
Description
Min
Max
Unit
SpecID
PORESET fall time
—
1
ms
A3.4
PORESET rise time
—
1
ms
A3.5
HRESET fall time
—
TBD
ns
A3.6
HRESET rise time
—
TBD
ns
A3.7
SRESET fall time
—
TBD
ns
A3.8
SRESET rise time
—
TBD
ns
A3.9
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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