參數(shù)資料
型號(hào)： MPC180LMB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, PQFP100
封裝： LQFP-100
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 356K
代理商： MPC180LMB
MOTOROLA
MPC180 Hardware Reference Manual
17
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Timing Analysis
Table 8 denes the terms used in the timing analysis.
7.1 Setup Time Margin and Maximum Propagation delays
The setup margin is dened as the difference between the clock period and the total setup time as shown
below:
tsetup_margin = tperiod - tsetup_total
(EQ 1)
The total setup time is the accumulation of the driver’s clock to output valid, the receiver’s input setup, the
clock skew and clock jitter and the offset between the processor and MPC180 clock:
tsetup_total = toa_source + tis_receiver + tclock_skew + tclock_offset
1
(EQ 2)
By substituting EQ2 into EQ1, the formula for calculating the setup margin becomes:
tsetup_margin = tperiod - toa_source - tis_receiver - tclock_skew - tclock_offset
1
(EQ 3)
NOTE
The value of the clock offset will be positive when the MPC180 is the
receiver and the offset will have a net subtractive effect. The value of the
clock offset will be negative when the host processor is the receiver and the
offset will have a net additive effect.
7.2 Hold Time Margin and Minimum Propagation Delays
The hold time margin can be dened as the driver’s output hold time, minus the receiver’s input hold, minus
the clock skew and clock jitter, plus the offset between the processor and MPC180 clock:
thold_margin = toh_source - tih_receiver - tclock_skew + tclock_offset
1
(EQ 4)
Table 8. Timing Analysis Terms
Term
Denition
tperiod
Clock period.
tis_receiver Input setup to the receiver. Time that an input must be valid before the rising edge of the clock;
specied by the receiver of the signal.
tih_receiver Input hold to the receiver. Time that an input must remain valid after the rising edge of the clock; specied by the receiver of
the signal.
toh_source Output hold from the source. Time from the rising edge of the clock until the output becomes invalid; specied by the source
of the output signal.
toa_source Maximum output access time from the source. Time from the rising edge of the clock until the last output becomes valid;
specied by the source of the output signal.
tclock_skew Clock skew (part to part and cycle to cycle)
tclock_offset An intentional offset between the MPC180 clock and the host processor clock. As a convention, the offset will be positive (+)
if the MPC180 clock arrives in time before the host processor clock and negative (-) if the MPC180 clock arrives in time after
the host processor clock.
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