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參數(shù)資料
| 型號： | MPC180LMB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, PQFP100 |
| 封裝： | LQFP-100 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大小： | 356K |
| 代理商： | MPC180LMB |
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16
MPC180 Hardware Reference Manual
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Timing Analysis
The only supported burst transfers are to the input buffer or from the output buffer when in 8260 mode. The
rst data transaction in 8260 mode requires two wait states and each subsequent data transaction requires
zero wait states.
Figure 10 shows a typical read cycle from the output FIFO and Figure 11 shows a typical write cycle to the
input FIFO.
Figure 10. MPC8260 Interface: Burst Read Cycle from Output FIFO
Figure 11. MPC8260 Interface: Burst Write Cycle to Input FIFO
7 System Timing Analysis
This section will perform a detailed timing analysis of the MPC180 interface to the MPC850, MPC860 and
MPC8260 communication processors. It will describe the methodology to calculate the setup and hold
margin, the relative timings of both the MPC180 and the host processor, how to intentionally add clock
offset between the processor and MPC180 to maximize timing margin, and nally, how to translate the
timing margin into the minimum and maximum length restrictions for use by the PCB layout engineer.
CLK
CS
R/W
BURST
A[18:29]
D[0:31]
LUPMWAIT
PSDVAL
CLK
CS
R/W
BURST
A[18:29]
D[0:31]
LUPMWAIT
PSDVAL
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