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參數(shù)資料
| 型號(hào)： | MPC180LMB |
| 廠(chǎng)商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, PQFP100 |
| 封裝： | LQFP-100 |
| 文件頁(yè)數(shù)： | 3/28頁(yè) |
| 文件大?。?/td> | 356K |
| 代理商： | MPC180LMB |
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MOTOROLA
MPC180 Hardware Reference Manual
11
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
6.5
IEEE 1149.1 AC Timing Specication
6.6 MPC180 and MPC8xx Timing Diagrams
A write cycle is dened as a transfer of data to the MPC180 from the host processor and a read cycle is
dened as a transfer of data from the MPC180 to the host processor. The processor initiates all data transfers,
acting as the bus master, and the MPC180 always acts as the bus slave. Data transfer is synchronous to the
main clock input and begins on the rising edge that TS and CS are asserted. At this time, the R/W signal
indicates whether the transaction is a read or a write and the address bus is decoded to select the destination
within the MPC180. The MPC180 holds the TA line high to signal the appropriate number of wait states and
then drives the signal low to indicate that valid data is on the bus. If TA is driven low during a read cycle,
the MPC180 is driving valid data; if TA is driven low during a write cycle, the MPC180 has captured valid
data.
shows a typical write cycle for the same interface.
Table 7. JTAG AC Timing Specications
Condition
Name
Min
Max
Units
TCK Cycle Time
tTHTH
60
—
nS
TCK Clock High Time
tTH
25
—
nS
TCK Clock Low Time
tTL
25
—
nS
TDO Access Time
tTLQV
110
nS
TRST pulse width
tTSRT
40
—
nS
Setup TImes
Capture
TDI
TMS
tCS
tDVTH
tMVTH
5
—nS
Hold TImes
Capture
TDI
TMS
tCH
tTHDX
tTHMX
13
14
—nS
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