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參數(shù)資料
| 型號： | MPC107ARX066L0 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, CBGA503 |
| 封裝： | 32.5 X 32.5 MM, CERAMIC, BGA-503 |
| 文件頁數(shù)： | 9/44頁 |
| 文件大?。?/td> | 553K |
| 代理商： | MPC107ARX066L0 |
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MPC107 Hardware Specifications (Rev B)
17
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Figure 8 shows Input Timing Diagram for Mode Select Signals.
Figure 8. Input Timing Diagram for Mode Select Signals
1.4.3.3 Output AC Timing Specication
Table 10 provides the processor bus AC timing specications for the MPC107. See Figure 6. and Figure 7..
Notes:
1
All memory and related interface output signal specications are specied from the VM = 1.4 V of the ris-
ing edge of the memory bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0 V) of the signal in
question. SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in
2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of
PCI_SYNC_IN). See Figure 6..
Table 10. Output AC Timing Specifications
At recommended operating conditions (See Table 2.) with GVdd = 3.3 V ± 5% and LVdd = 3.3 V ± 5%
Nu
m
Characteristic3,6
Min
Max
Units
Notes
12a
PCI_SYNC_IN to Output Valid, 66 MHz PCI, with MCP pulled-
down to logic 0 state. See Table 11..
6.0
ns
2,4
PCI_SYNC_IN to Output Valid, 33 MHz PCI, with MCP in the
default logic 1 state. See Table 11..
8.0
ns
2,4
12b
SDRAM_SYNC_IN to Output Valid
(For Memory Bus Control & Data Signals)
5.5
ns
1
12c
SDRAM_SYNC_IN to Output Valid (For All Others)
TBD
ns
1
12d
SDRAM_SYNC_IN to Output Valid (For I2C)
TBD
ns
1
12e
SDRAM_SYNC_IN to Output Valid
(For Processor Bus Control & Data Signals)
TBD
ns
1
13a
Output Hold, 66 MHz PCI, with MCP and CKE pulled-down to logic
0 states. See Table 11..
1.0
ns
2,4,5
Output Hold, 33 MHz PCI, with MCP in the default logic 1 state and
CKE pulled-down to logic 0 state. See Table 11..
2.0
ns
2,4,5
13b
Output Hold (For All Others)
1
ns
1
14a
PCI_SYNC_IN to Output High Impedance (For PCI)
TBD
ns
2,4
14b
SDRAM_SYNC_IN to Output High Impedance (For All Others)
TBD
ns
1
VM
VM = Midpoint Voltage (1.4V)
11b
MODE PINS
10e
HRESET
2.0 V
0.8 V
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