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參數(shù)資料
| 型號： | MPC107ARX066L0 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, CBGA503 |
| 封裝： | 32.5 X 32.5 MM, CERAMIC, BGA-503 |
| 文件頁數(shù)： | 43/44頁 |
| 文件大?。?/td> | 553K |
| 代理商： | MPC107ARX066L0 |
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8
MPC107 Hardware Specifications (Rev B)
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Figure 2 shows the Supply Voltage Sequencing and Separation Cautions.
Figure 2. Supply Voltage Sequencing and Separation Cautions
OVdd/BVdd/GVdd/(LVdd@3.3V - - - -)
Vdd/AVdd/LAVdd
LVdd@5V
Time
3.3V
5V
2.5V
0
6
9
8
9
5,7
DC
P
o
w
er
Supply
V
oltage
Voltage
Regulator
Delay2
Reset
Configuration Pins
HRESET
PLL
Relock
Time3
100 s
9 external memory
asserted 255
external memory
HRESET
Vdd Stable
Power Supply Ramp Up2
See Note 1 below.
clock cycles3
clock cycles setup time4
VM = 1.4 V
Notes:
1. Numbers associated with waveform separations correspond to caution numbers listed in Table 2.
2. Refer to Paragraph 1.7.2 Power Supply Voltage Sequencing for additional information on this topic.
3. Refer to Table 8. for additional information on PLL Relock and reset signal assertion timing requirements.
4. Refer to Table 9. for additional information on reset conguration pin setup timing requirements.
5. HRESET and HRESET_CPU must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN
clock cycle for the device to be in the non-reset state.
6. HRESET_CPU negates 217 memory clock cycles after HRESET negates.
HRESET_CPU
VM = 1.4 V
Maximum rise time must be less than
one external memory clock cycle5
6
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