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參數(shù)資料
| 型號： | MP3276AP |
| 廠商： | EXAR CORP |
| 元件分類： | ADC |
| 英文描述： | Fault Protected 16 Channel, 12-Bit Data Acquisition Subsystem |
| 中文描述： | 16-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大小： | 170K |
| 代理商： | MP3276AP |
MP3276
9
Rev. 4.00
Figure 3. Load Circuit for Data
Access Time Test
3k
C
L
a. High-Z to V
ON
DB
N
3k
b. High-Z to V
OL
+5 V
Figure 4. Load Circuit for
Bus Relinquish Time Test
3k
10pF
a. V
ON
to High-Z
3k
10pF
b. V
OL
to High-Z
+5 V
N
DB
N
DB
N
DB
C
L
C
L
Figure 5. Load Circuit for WR to STS Delay
DGND
STL, STS
Serial Data Output Mode (PXS = 0)
The MP3276 output data is available in serial form when PXS
= 0 prior to the RD high-to-low transition. When PXS = 0, the
DB11/SDO pin functions as the serial data output. The
DB0/SDC pin functions as the serial clock input and all other
data outputs are 3-stated.
The serial data output sequence is MSB (DB11) first to LSB
(DB0) last. The MSB (DB11) data bit appears at DB11/SDO
when STS goes low. The second most significant bit appears at
DB11/SDO on the next DB0/SDC high-to-low transition. The
LSB (DB0) is present at DB11/SDO on the 11th SDC high-to-low
transition.
The control pin functions (ADEN, CS, WR, and RD) are the
same as the parallel mode of operation. Further information re-
garding serial control and timing is shown in Figure 6.,Table 4.
and Table 5.
For a minimum interconnect serial environment, the channel
address state can be generated in at least two ways, using an
address counter, or using an address serial to parallel converter.
WR can then be used as the counter clock or shift register load
signal as well as the A/D converter start convert signal on the ris-
ing edge. (Note that the falling edge loads the address present at
the address port.)
SDC
DB11/SDO
Figure 6. Serial Data Mode Timing
DB11 (MSB)
DB10
t
21
t
22
SDC should be in a high state during the STS high period. SDC can make the first high to low transition after t
. In normal use it is
assumed that PXS is hardwired low. However, if the mode of operation is changed, PXS must go low prior to RD going low.
t
20
STS
See Table 4
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