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參數(shù)資料
| 型號： | MP3276AP |
| 廠商： | EXAR CORP |
| 元件分類： | ADC |
| 英文描述： | Fault Protected 16 Channel, 12-Bit Data Acquisition Subsystem |
| 中文描述： | 16-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 170K |
| 代理商： | MP3276AP |
MP3276
10
Rev. 4.00
Table 4. Serial Data Output Mode Timing (See Figure 6.)
25
°
C
Tmin to
Tmax
Limits
Comments/Test Conditions
STS low to SDO (DB11) Valid,
RD = 0
Minimum clock high pulse width
SDC low to data valid delay
t
20
50
50
ns max
Load Ckt 4 of Figure 3.
t
21
t
22
50
150
200
80
200
250
ns max
ns max
ns max
Load ckt of Figure 3. C
L
= 20pF
Load ckt of Figure 3. C
L
= 100pF
Serial Data Output Timing
Time
Interval
Note 1: If RD = 1, data outputs remain high impedance. It is recommended that RD will not change during a conver-
sion in order to reduce noise. It is further recommended that RD = 1 during conversion to reject any noise present on
the data bus.
Table 5. Logic Truth Table – Serial Data Output Mode
CS
WR
RD
ADEN
Data
STL
STS
Comments
1
0
0
0
X
↓
0
0
X
X
↓
↓
X
1
1
1
X
X
0
1
––
Hi-Z
Hi-Z
Hi-Z
0
0
0
↑
0
0
0
0
X
X
X
X
No Operation
Serial mode enabled (1)
No operation if ADEN = 0
Input MUX channel selected, STL
set on falling edge of WR
MUX select disabled
Start convert on WR rising edge
Start convert on STL falling edge
STS goes low at end of conversion
0
0
0
0
0
0
0
0
0
↑
1
1
1
1
1
1
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
0
↓
0
0
↑
↑
↓
X
X
X
X
PXS
ADC Channel Select and Start Convert
DB0/SDC
0
0
1
↓
X
––
0
0
1
Serial output (DB11/SDO) and
serial clock input (DB0/SDC)
enabled
MSB data available at DB11/SDO
Next significant bit shifted out to
DB11/SDO
No Operation
No Operation
Next significant bit shifted out to
DB11/SDO
Data outputs/SDC input disabled
Data outputs/RD disabled when
STS = 1
STL, MUX select disabled when
ADEN = 0
New data appears at DB11/SDO
on falling edge of STS
0
0
0
0
X
X
X
0
X
X
MSB (DB11)
DB10
0
0
0
0
1
↓
0
0
0
0
0
0
X
X
X
0
0
0
X
X
X
DB10
DB10
DB9
0
0
0
0
0
0
0
↑
↓
0
0
0
X
X
1
↑
X
X
X
Hi-Z
Hi-Z
0
0
0
1
X
X
0
X
0
0
Hi-Z
0
↑
1
0
0
0
X
MSB (DB11)
0
↓
1
Read ADC Data (See Table 4. and Figure 6.)
Table 6. Key Output Codes vs. Input Voltage (2’s Complement Code)
2’s Complement Output Code (Hexidecimal)
Ideal Transition Voltage
+FS – 1 1/2 LSB
0 V +1/2 LSB
0 V –1/2 LSB
–FS +1/2 LSB
0111
0000
1111
1000
1111
0000
1111
0000
1110 (7fe) to
0000 (000) to
1111 (fff) to
0000(800) to
0111
0000
0000
1000
1111
0000
0000
0000
1111 (7ff)
0001 (001)
0000 (000)
0001 (801)
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