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參數(shù)資料
| 型號： | MP3276AP |
| 廠商： | EXAR CORP |
| 元件分類： | ADC |
| 英文描述： | Fault Protected 16 Channel, 12-Bit Data Acquisition Subsystem |
| 中文描述： | 16-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 170K |
| 代理商： | MP3276AP |
MP3276
11
Rev. 4.00
APPLICATION INFORMATION
The MP3276 is a complete A/D converter system, with its
own built-in reference and clock. It may be used by itself (“stand-
alone” operation), or it may be interfaced with a microprocessor
which can control both conversion and formatting of output.
Successful application of the MP3276 requires careful atten-
tion to four main areas:
1)
2)
3)
4)
Physical layout.
Connection/Trimming according to mode of operation.
Conditioning of input signals.
Control and Timing considerations.
Physical Layout
The 12-bit accuracy of the MP3276 represents a dynamic
range of 72dB. Precautions must be taken to avoid any interfer-
ing signals, whether conducted or radiated, to assure that this is
not degraded.
Avoid placing the chip and its analog signals near logic
traces. In general, using a double sided printed circuit
card with a good ground plane on the component side is
recommended. Routing analog signals between ground
traces will help isolate digital control logic. If these lines
cross, do so at right angles. The GND Ref. is the positive
terminal of the MUX/Instrumentation amplifier and will
provide common mode noise rejection. It should be
close to and shielded together with the channel inputs in
order to take advantage of this feature.
Power supplies should be quiet and well regulated.
Grounds should be tied together at the package and
back to the system ground with a single path. Bypass the
supplies at the device with a 0.01 to 0.1
μ
F ceramic cap
and a 10-47
μ
F tantalum type, in parallel.
“Stand-Alone” Operation
The MP3276 can be used in “stand-alone” operation, which is
useful in systems not requiring full computer bus interface capa-
bility. This operation is available for either parallel or serial mode.
For this operation, CS = 0, ADEN = 1, and conversion is con-
trolled by WR. The 3-state buffers are enabled when RD goes
low. There are two possible conditions that the 3-state buffers
could be in during a conversion. If RD goes low prior to WR, the
output buffers are enabled and the data from the previous con-
version is available at the outputs during STL = 1. At the end of
the present conversion which is initiated at the rising edge of
WR, STS returns low and the new conversion result is placed on
the output data buffers.
If WR goes low prior to RD, the data buffers remain in a high
impedance state and conversion is initiated at the rising edge of
WR. Upon the end of the conversion the STS returns low and
the conversion result is placed on the output data buffers. It is
imperative that RD or WR not change during a conversion to in-
sure that errors will not occur.
Ground Reference
The ground reference pin can be used for remote ground
sensing of a common mode input signal with a maximum 6 V p-p
around AGND.
This common input can also be used to dither each input’s
“zero”. By averaging multiple conversions digitally, higher reso-
lution for each input conversion can be obtained. Patterns for
this dither can be a ramp, a stair step, or white noise.
COMP
S
A
R
VDAC
12
130k
26k
130k
26k
1 of 16
GND Ref.
Figure 7. Equivalent Input Circuit
1/2
V
REF
Quasi Differential Sampling
Method 1
For remote ground sensing where the remote ground does
not change more than 3 V from the A/D ground, connect GND
Ref to the remote ground.
Method 2
Where Method 1 applies to each channel or group of chan-
nels, add a mux to allow connecting the appropriate ground to
GND Ref.
Method 3
Use two parts. Tie both GND Ref pins together and connect
this node to the “common” remote GND. Control the sample
point by connecting each STL through an “OR” gate whose out-
put is “NAND” connect with WR (inverted WR). Use this output
as WR to both WR inputs. By controlling the WR, sample delay
differences between the two converters is minimized. Two parts
from the same date code will further minimize this difference.
Treat one A/D as the (+) terminal and the other as the (–) termi-
nal of the differential signal. Now the difference can be taken
digitally.
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