參數(shù)資料
型號: MN89306
廠商: PANASONIC CORP
元件分類: 顯示控制器
英文描述: 800 X 600 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP128
封裝: 18 X 18 MM, PLASTIC, LQFP-128
文件頁數(shù): 9/47頁
文件大小: 487K
代理商: MN89306
LSIs for Display
MN89306
17
s Pin Descriptions (continued)
6) Chip Settings
Pin Name
I/O
Level
Function
RESET
I
5 VTTL
RESET(ISA, 386, 486, RISC)
When a high level is input to this pin, the chip is reset to its initial state. When 386
mode is used for the host type, this reset signal is also used for clock phase adjustment.
Note that this pin functions as an active-high signal.
MA[2 : 0]
I
CMOS
HOST type
The MA[2:0] pins are set to input mode during the reset period. When these pins
are in input mode, they are used to decide the type of the connected host. Settings
other than those listed in the table are not permitted.
MA[2 : 0]
Host type
0
ISA
0
1
386SX
0
1
0
386DX
0
1
486
1
0
Reserved
1
0
1
RISC CPU (RDY# interface)
1
0
RISC CPU (WAIT# interface)
1
0
Reserved
XIN/XO
I/O
CMOS
Clock In/Out
Chip clock input and output. Connect a crystal oscillator between these pins. The
input frequency must be in the range 14 MHz to 33 MHz.
EXTCLK
I
CMOS
External MCLK
Used for IC testing. This pin must be held at the ground level during normal
operation.
MINTEST
I
CMOS
Used for IC testing. These pin must be held at the ground level during normal
TEST
I
operation.
PLLTEST
I/O
Used for PLL testing. This pin must be held at the ground level during normal
operation.
7) Power Supply
Pin Name
I/O
Level
Function
VDD
Digital system power supply (3.3 V)
GND
Digital system power supply (GND)
VREF5
5 V input pin power supply (4.75 V to 5.25 V)
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