參數(shù)資料
型號： MN89306
廠商： PANASONIC CORP
元件分類： 顯示控制器
英文描述： 800 X 600 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP128
封裝： 18 X 18 MM, PLASTIC, LQFP-128
文件頁數(shù)： 16/47頁
文件大?。?/td> 487K
代理商： MN89306
LSIs for Display
MN89306
23
s Electrical Characteristics (continued)
4. AC Characteristics (continued)
1) RESET Signal Timing (Applies to the ISA, local, and RISC CPU buses)
No.
Descriptions
Min
Max
Unit
1
RESET high-level period
1
A
2
RESET setup time
5
ns
3
RESET hold time
8
ns
4
MA input switching time
4XIN
+15
ns
5
MA output switching time
4XIN
+15
ns
6
MA valid data input setup time
0
ns
7
MA valid data input hold time
3XIN
+12
ns
RESET
XIN
MA
Output
Input
Valid data
1
2
4
5
7
6
3
2) XIN Timing
No.
Descriptions
Min
Max
Unit
1
XIN rise time (external clock signal mode)
4ns
2
XIN fall time (external clock signal mode)
4ns
3
XIN high-level period (external clock signal mode)
10
ns
4
XIN low-level period (external clock signal mode)
10
ns
5
XIN period
30
ns
XIN
5
3
4
1
2
Note) The XIN clock determines the memory control timing and the LCD control timing.
Determine the XIN clock period based on the specifications of the DRAM and LCD panel used.
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