參數(shù)資料
型號(hào): MN89306
廠商: PANASONIC CORP
元件分類: 顯示控制器
英文描述: 800 X 600 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP128
封裝: 18 X 18 MM, PLASTIC, LQFP-128
文件頁數(shù): 24/47頁
文件大?。?/td> 487K
代理商: MN89306
MN89306
LSIs for Display
30
No.
Descriptions
Min
Max
Unit
1
RS[2:0] and WD[7:0] setup time
4CLK
10
ns
2
RS[2:0] and WD[7:0] hold time
10CLK
10
ns
3
WR active time
6CLK
10
ns
4
WR inactive time
8CLK
10
ns
10) External RAMDAC Register Write Timing
Note) 1. CLK in the table is a period time of MCLK in ISA mode, CCLK in RISC CPU mode, CCLK in local bus 486 mode, and
CCLK
× 2 in local bus 386 mode.
2. Values listed in the table apply when the external load capacitor is 30 pF.
RS0 to 2
WD0 to 7
WR
12
34
No.
Descriptions
Min
Max
Unit
12
RDY# and WAIT# output delay time
3
25
ns
13
RDY# low-level output and WAIT# high-level output delay time
10
28
ns
14
RDY# and WAIT# hold time
3
ns
15
Delay time from A[25:1], CS# , or CCLK to the RDY# or WAIT#
25
ns
output high-impedance state.
16
RD#, WE1, and WE0 command inactive time
1CLK
+6
ns
s Electrical Characteristics (continued)
4. AC Characteristics (continued)
9) RISC CPU Timing (continued)
Note) 1. : The wait time differs depending on the chip status.
2. CLK in the table refers to one clock period of CCLK.
3. Values listed in the table apply when the external load capacitor is 50 pF. The output delay times will differ depending on
the external load capacitor.
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