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參數(shù)資料
| 型號： | MMDF3N03HDR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | JFETs |
| 英文描述： | 2.8 A, 30 V, 0.09 ohm, 2 CHANNEL, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | SO-8 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 281K |
| 代理商： | MMDF3N03HDR2 |
MMDF3N03HD
5
Motorola TMOS Power MOSFET Transistor Device Data
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance – Gen-
eral Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(R
θJC).
A power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem-
perature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 9). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
Figure 8. Capacitance Variation
C,
CAP
ACIT
ANCE
(pF)
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
V
GS
,GA
TE–T
O–SOURCE
VOL
TAGE
(VOL
TS)
Qg, TOTAL GATE CHARGE (nC)
t,
TIME
(ns)
RG, GATE RESISTANCE (OHMS)
1000
1
100
10
1
I S
,SOURCE
CURRENT
(AMPS)
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
1.0
1.5
2.0
3.0
2.5
0.5
0.55
0
2
4
6
8
ID = 3 A
TJ = 25°C
VGS
6
3
0
12
9
24
18
12
6
0
VDS
QT
Q1
Q2
Q3
10
12
10
0
10
15
25
VGS
VDS
TJ = 25°C
VDS = 0 V VGS = 0 V
1000
800
600
400
200
0
20
Ciss
Coss
Crss
5
Ciss
Crss
30
V
DS
,DRAIN–T
O–SOURCE
VOL
TAGE
(VOL
TS)
VDD = 15 V
ID = 3 A
VGS = 10 V
TJ = 25°C
td(on)
tr
Figure 9. Gate–to–Source and
Drain–to–Source Voltage versus Total Charge
Figure 10. Resistive Switching Time Variation
versus Gate Resistance
Figure 11. Diode Forward Voltage
versus Current
0.5
TJ = 25°C
VGS = 0 V
0.6
0.65
0.7
0.75
0.8
0.85
100
10
td(off)
tf
1200
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