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參數(shù)資料
| 型號： | MM24128-BWMW6T |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | EEPROM |
| 英文描述： | 256/128 Kbit Serial IC Bus EEPROM Without Chip Enable Lines |
| 中文描述： | 一百二十八分之二百五十六千位串行IC總線的EEPROM芯片使能線無 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 135K |
| 代理商： | MM24128-BWMW6T |
5/17
M24256, M24128
There are two modes both for read and write.
These are summarized in Table 4 and described
later. A communication between the master and
the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 5) is sent first, followed by the Least significant
Byte (Table 6). Bits b15 to b0 form the address of
the byte in memory. Bit b15 is treated as a Don’t
Care bit on the M24256 memory. Bits b15 and b14
are treated as Don’t Care bits on the M24128
memory.
Table 4. Operating Modes
Note: 1. X =
V
IH
or V
IL
.
Mode
RW bit
WC
1
Data Bytes
Initial Sequence
Current Address Read
1
X
1
START, Device Select, RW
= ‘1’
Random Address Read
0
X
1
START, Device Select, RW = ‘0’, Address
1
X
reSTART, Device Select, RW = ‘1’
Sequential Read
1
X
≥
1
Similar to Current or Random Address Read
Byte Write
0
V
IL
1
START, Device Select, RW = ‘0’
Page Write
0
V
IL
≤
64
START, Device Select, RW
= ‘0’
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
S
S
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN
WC
S
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN 1
WC
DATA IN 2
AI01120C
PAGE WRITE
(cont'd)
WC (cont'd)
S
DATA IN N
ACK
ACK
ACK
NO ACK
R/W
ACK
ACK
ACK
NO ACK
R/W
NO ACK
NO ACK
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