參數(shù)資料
型號： ML9044A-XXACVWA
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 顯示控制器
英文描述： 17 X 120 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC189
封裝： GOLD BUMP, DIE-189
文件頁數(shù)： 32/65頁
文件大?。?/td> 726K
代理商： ML9044A-XXACVWA
PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
37/64
7) CGRAM Address Setting
RS1
1
RS0
0
R/W
0
DB7
0
DB6
1
DB5
C5
DB4
C4
DB3
C3
DB2
C2
DB1
C1
DB0
C0
Instruction code:
This instruction sets the CGRAM address to the data represented by the bits C5 to C0 (binary).
The CGRAM addresses are valid until DDRAM or ABRAM addresses are set.
The CPU writes or reads character patterns starting from the one represented by the CGRAM address bits C5 to
C0 set in the instruction code at that time.
Note: The execution time of this instruction is 37
s at an oscillation frequency (OSC) of 270 kHz.
8) DDRAM Address Setting
RS1
1
RS0
0
R/W
0
DB7
1
DB6
D6
DB5
D5
DB4
D4
DB3
D3
DB2
D2
DB1
D1
DB0
D0
Instruction code:
This instruction sets the DDRAM address to the data represented by the bits D6 to D0 (binary).
The DDRAM addresses are valid until CGRAM or ABRAM addresses are set.
The CPU writes or reads character codes starting from the one represented by the DDRAM address bits D6 to
D0 set in the instruction code at that time.
In the 1-line mode (the “N” bit is “0”), the DDRAM address represented by bits D6 to D0 (binary) should be in
the range “00” to “4F” in hexadecimal.
In the 2-line mode (the “N” bit is “1”), the DDRAM address represented by bits D6 to D0 (binary) should be in
the range “00” to “27” or “40” to “67” in hexadecimal.
If an address other than above is input, the ML9044A cannot properly write a character code in or read it from
the DDRAM.
Note: The execution time of this instruction is 37
s at an oscillation frequency (OSC) of 270 kHz.
9) DDRAM/ABRAM/CGRAM Data Write
RS1
1
RS0
1
R/W
0
DB7
E7
DB6
E6
DB5
E5
DB4
E4
DB3
E3
DB2
E2
DB1
E1
DB0
E0
Instruction code:
A character code (E7 to E0) is written to the DDRAM, Display-ON data (E7 to E0) to the ABRAM or a character
pattern (E7 to E0) to the CGRAM.
The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.
After data is written, the address counter (ADC) is incremented or decremented as set by the Entry Mode
Setting instruction (see 3).
Note: The execution time of this instruction is 37
s at an oscillation frequency (OSC) of 270 kHz.
相關(guān)PDF資料
PDF描述
ML9203-01GA 16 X 35 DOTS FLUORESCENT DSPL CTRL, PQFP100
ML9206-XXGS-BK 16 X 37 DOTS FLUORESCENT DSPL CTRL, PQFP64
ML9206-XXGS-K 16 X 37 DOTS FLUORESCENT DSPL CTRL, PDSO64
ML9206-XXMB 36 X 16 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PDSO64
ML9206-XXGA 36 X 16 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP64
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ML9044A-XXBCVWA 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:DOT MATRIX LCD CONTROLLER DRIVER
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