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參數(shù)資料
| 型號(hào)： | ML9042-21DVWA |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 顯示控制器 |
| 英文描述： | 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC233 |
| 封裝： | DIE-233 |
| 文件頁(yè)數(shù)： | 58/58頁(yè) |
| 文件大?。?/td> | 558K |
| 代理商： | ML9042-21DVWA |
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FEDL9042-01
OKI Semiconductor
ML9042-xx
9/58
(GND = 0 V, VDD = 2.7 to 5.5 V, Ta = –40 to +85°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Applicable
pins
Voltage Multiplier
Input Voltage
VMUL
Note 7
1.8
—
2.75
V
VIN
1/5
bias
4.3
—
(VDD–VIN)
× 2
Voltage Multiplier
Output Voltage
VOUT
VDD = 2.7 V, VIN = 2.25 V
f = 175 kHz
A capacitor for the voltage
multiplier = 1 to 4.7
F
VOUT load current = 54 A
BE = “H”
Applied to LCD bias
resistance of 10 k
(TYP)
only
1/4
bias
4.3
—
(VDD–VIN)
× 2
V
VOUT
VLCD1
1/5
bias
2.7
—
5.5
Bias Voltage for
Driving LCD
VLCD2
V0–GND
Note 8
1/4
bias
2.7
—
5.5
V
V0
Note 1:
Applied to the voltage drop occurring between any of the V0, V1, V4 and GND pins and any of
the common pins (COM1 to COM17) when the current of 4 A flows in or flows out at one
common pin.
Also applied to the voltage drop occurring between any of the V0, V2, V3A (V3B) and GND pins
and any of the segment pins (SEG1 to SEG100) when the current of 4 A flows in or flows out at
one segment pin.
The current of 4
A flows out when the output level is V
DD or flows in when the output level is
V5.
Note 2:
Applied to the current flowing into the VDD pin when the external clock (fOSC2 = fin = 270 kHz) is
fed to the internal Rf oscillation or OSC1 under the following conditions:
VDD = V0 = 5 V
GND = 0 V,
V1, V2, V3A (V3B) and V4: Open
E/SHTB and BE: “L” (fixed)
Other input pins: “L” or “H” (fixed)
Other output pins: No load
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