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參數(shù)資料
| 型號： | ML67Q5003LA |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PBGA144 |
| 封裝： | 11 X 11 MM, 0.80 MM PITCH, PLASTIC, LFBGA-144 |
| 文件頁數(shù)： | 24/25頁 |
| 文件大?。?/td> | 233K |
| 代理商： | ML67Q5003LA |
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
7/24
Pin
Primary Function
Secondary Function
LQFP
BGA
Symbol
I/O
Description
Symbol
I/O
Description
41
L4
VDD_IO
VDD
I/O power supply
—
42
M3
XA[10]
O
External address output
—
43
N4
XA[11]
O
External address output
—
44
L5
XA[12]
O
External address output
—
45
M4
XA[13]
O
External address output
—
46
N5
XA[14]
O
External address output
—
47
K5
GND
—
48
M5
XA[15]
O
External address output
—
49
N6
XA[16]
O
External address output
—
50
M6
XA[17]
O
External address output
—
51
K6
GND
—
52
L6
XA[18]
O
External address output
—
53
M7
PIOC[2]
I/O
General port (with interrupt function)
XA[19]
O
External address output
54
K7
VDD_IO
VDD
I/O power supply
—
55
L7
PIOC[3]
I/O
General port (with interrupt function)
XA[20]
O
External address output
56
N7
PIOC[4]
I/O
General port (with interrupt function)
XA[21]
O
External address output
57
L8
PIOC[5]
I/O
General port (with interrupt function)
XA[22]
O
External address output
58
K8
VDD_CORE
VDD
CORE power supply
—
59
M8
PIOC[6]
I/O
General port (with interrupt function)
XA[23]
O
External address output
60
M9
PIOC[7]
I/O
General port (with interrupt function)
XWR
O
Transfer direction of
external bus
61
N8
XOE_N
O
Output enable (excluding SDRAM)
—
62
K9
VDD_IO
VDD
I/O power supply
—
63
M10
XWE_N
O
Write enable
—
64
N9
XBWE_N[0]
O
Byte write enable (LSB)
—
65
L9
XBWE_N[1]
O
Byte write enable (MSB)
—
66
L10
XROMCS_N
O
External ROM chip select
—
67
N10
XRAMCS_N
O
External RAM chip select
—
68
M11
XIOCS_N[0]
O
IO chip select 0
—
69
K10
GND
—
70
N11
XIOCS_N[1]
O
IO chip select 1
—
71
M12
XIOCS_N[2]
O
IO chip select 2
—
72
N12
XIOCS_N[3]
O
IO chip select 3
—
73
N13
PIOD[6]
I/O
General port (with interrupt function)
XDQM[1]/XCAS
_N[1]
O
INPUT/OUTPUT
mask/CAS (MSB)
74
M13
PIOD[7]
I/O
General port (with interrupt function)
XDQM[0]/XCAS
_N[0]
O
INPUT/OUTPUT
mask/CAS (LSB)
75
L11
PIOB[0]
I/O
General port (with interrupt function)
DREQ[0]
I
DMA request signal (CH0)
76
L13
PIOB[1]
I/O
General port (with interrupt function)
DREQCLR[0]
O
DREQ Clear Signal
(CH0)
77
K11
VDD_IO
VDD
I/O power supply
—
78
L12
PIOB[2]
I/O
General port (with interrupt function)
DREQ[1]
I
DMA request signal
(CH1)
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