參數(shù)資料
型號： ML60851D
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： USB Device Controller
中文描述： USB設(shè)備控制器
文件頁數(shù)： 69/82頁
文件大?。?/td> 705K
代理商： ML60851D
FEDL60851D-01
1
Semiconductor
ML60851D
69/82
(5) Transmit packet ready interrupts (EP1, EP2, EP3)
These interrupts are generated when it is possible for the local MCU to write the data packet to be sent to the
USB bus from the corresponding EP.
Operation
Source of operation
ML60851D
Description (conditions, responses, etc.)
(1) In the case of bulk transfer and interrupt transfer
When the respective EP has been set for transmission,
the transmit packet ready bit of the corresponding EP is
de-asserted when it is possible to write the transmit
data into the FIFO.
At this time, an interrupt is generated if the
corresponding EP transmit packet ready interrupt
enable bit (INTENBL1) has been asserted.
For the second and subsequent packets, in addition to
this condition, before the interrupt is generated, it is
necessary for an ACK response to come from the host
for the packet that has just been sent.
(1) In the case of bulk transfer and interrupt transfer
After the one packet of the corresponding EP transmit
data has been written in EPnTXFIFO, write a “1” into the
corresponding transmit packet ready bit. This puts the
ML60851D in a state in which it can transmit the data
and the
INTR
pin is de-asserted at the same time.
Even when the number of bytes in the write data is less
than the maximum packet size, it is possible to end the
pocket transmission by writing a “1” into the transmit
packet ready status bit.
Transmit packet ready
interrupt generation
End of transmit packet ready
interrupt
Local MCU (firmware)
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