參數(shù)資料
型號(hào)： ML60851D
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： USB Device Controller
中文描述： USB設(shè)備控制器
文件頁(yè)數(shù)： 10/82頁(yè)
文件大?。?/td> 705K
代理商： ML60851D
PEDL60851D-01
1
Semiconductor
ML60851D
10/82
End Point 2 Transmit FIFO (EP2TXFIFO)
Read address
Write address
—
C2h
D7
x
x
D6
x
x
D5
x
x
EP2 Transmit data (W)
D4
x
x
D3
x
x
D2
x
x
D1
x
x
D0
x
x
After a hardware reset
After a bus reset
Definition
The EP2 transmit data can be written in by writing to the address C2h. When EP2 has been set for bulk
transmission (BULK IN), The local MCU should write the transmit data in EP1TXFIFO when the ML60851D
issues an EP2 packet ready interrupt request. It is possible to write the packet data successively by writing
continuously. When the data transfer direction of EP2 is set as “Receive”, all accesses to this address will be
invalid.
The EP2 TXFIFO is cleared under the following conditions:
1. When an ACK is received from the host for the data transmission from EP2.
2. When the local MCU writes a “1” in the EP2FIFO clear bit (CLRFIFO(2)).
End Point 3 Transmit FIFO (EP3TXFIFO)
Read address
Write address
—
C3h
D7
x
x
D6
x
x
D5
x
x
EP3 Transmit data (W)
D4
x
x
D3
x
x
D2
x
x
D1
x
x
D0
x
x
After a hardware reset
After a bus reset
Definition
The EP3 transmit data can be written in by writing to the address C3h. Make the local MCU write the transmit data
in EP3TXFIFO when the ML60851D issues an EP3 packet ready interrupt request. It is possible to write the
packet data successively by writing continuously.
The EP3 TXFIFO is cleared under the following conditions:
1. When an ACK is received from the host for the data transmission from EP3.
2. When the local MCU writes a “1” in the EP3FIFO clear bit (CLRFIFO(3)).
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