參數(shù)資料
型號: MK60N512VMC100
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA121
封裝: 8 X 8 MM, MAPBGA-121
文件頁數(shù): 20/72頁
文件大小: 1812K
代理商: MK60N512VMC100
Table 13. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Iintf
Internal reference (fast clock) current
TBD
A
tirefstf
Internal reference startup time (fast clock)
TBD
s
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
kHz
FLL
ffll_ref
FLL reference frequency range
31.25
39.0625
kHz
fdco
DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
20
20.97
25
MHz
2, 3
Mid range (DRS=01)
1280 × ffll_ref
40
41.94
50
MHz
Mid-high range (DRS=10)
1920 × ffll_ref
60
62.91
75
MHz
High range (DRS=11)
2560 × ffll_ref
80
83.89
100
MHz
fdco_t_DMX3
2
DCO output
frequency
Low range (DRS=00)
732 × ffll_ref
23.99
MHz
4, 5
Mid range (DRS=01)
1464 × ffll_ref
47.97
MHz
Mid-high range (DRS=10)
2197 × ffll_ref
71.99
MHz
High range (DRS=11)
2929 × ffll_ref
95.98
MHz
Jcyc_fll
FLL period jitter
TBD
ps
Jacc_fll
FLL accumulated jitter of DCO output over a 1s
time window
TBD
ps
tfll_acquire
FLL target frequency acquisition time
1
ms
PLL
fvco
VCO operating frequency
48.0
100
MHz
Ipll
PLL operating current
PLL @ 96 MHz (fosc_hi_1=8MHz,
fpll_ref=2MHz, VDIV multiplier=48)
950
A
fpll_ref
PLL reference frequency range
2.0
4.0
MHz
Jcyc_pll
PLL period jitter
400
ps
Jacc_pll
PLL accumulated jitter over 1s window
TBD
ps
Table continues on the next page...
Peripheral operating requirements and behaviors
K60 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
27
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