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參數(shù)資料
| 型號： | MK2731-01GTR |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 66.66 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 183K |
| 代理商： | MK2731-01GTR |
MK2731-01
LOW COST VCXO
VCXO
IDT / ICS LOW COST VCXO
2
MK2731-01
REV E 021804
Pin Assignment
Output Clock Select Table
(All OFF outputs are stopped low)
Pin Descriptions
12
1
11
2
10
3
9
X2
4
X1
5
VDD
6
NC
7
VIN
8
GND
S2
VDD
GND
CLK2
S0
OE
S1
16
15
14
13
CLK1
VDD
16-pin narrow (150 mil) SOIC
Input
S2
S1
S0
CLK1
CLK2
10
0
40
80
10
0
1
40
OFF
13.5
0
1
0
40
OFF
13.5
0
1
27
54
13.5
1
0
33.33
66.66
13.5
1
0
1
24.576
49.152
—
1
0
Test use
13.5
1
32
64
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X2
Output
Crystal connection. Connect to a 10 or 13.5 MHz pullable crystal.
2
X1
Input
Crystal connection. Connect to a 10 or 13.5 MHz pullable crystal.
3
VDD
Power
Connect to +5 V.
4
VIN
Input
Voltage input to VCXO. Zero to 3 V signal which controls the
VCXO frequency.
5
GND
Power
Connect to ground.
6
GND
Power
Connect to ground.
7
OE
Input
Output Enable. Active high. Tri-states both outputs when low.
8
CLK1
Output
Clock output 1 determined by status of S2, S1, and S0. See table
above.
9
S0
Input
Fixed Clock Select 0. Selects outputs per table above.
10
S1
Input
Fixed Clock Select 1. Selects outputs per table above.
11
CLK2
Output
Clock output 2 determined by status of S2, S1, and S0. See table
above.
12
GND
Power
Connect to ground.
13
VDD
Power
Connect to +5 V.
14
S2
Input
Fixed Clock Select 2. Selects outputs per table above.
15
NC
--
No connect.
16
VDD
Power
Connect to +5 V.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2731-03C | 制造商:ICS 制造商全稱:ICS 功能描述:MPEG Audio Clock Synthesizer |
| MK2731-03S | 制造商:ICS 制造商全稱:ICS 功能描述:MPEG Audio Clock Synthesizer |
| MK2731-03STR | 制造商:ICS 制造商全稱:ICS 功能描述:MPEG Audio Clock Synthesizer |
| MK2731-04C | 制造商:ICS 制造商全稱:ICS 功能描述:MPEG Audio Clock |
| MK2731-04S | 制造商:ICS 制造商全稱:ICS 功能描述:MPEG Audio Clock |
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