參數(shù)資料
型號(hào): MK20N512VMD100R
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144
封裝: 13 X 13 MM, MAPBGA-144
文件頁數(shù): 59/74頁
文件大?。?/td> 1849K
代理商: MK20N512VMD100R
Table 43. I2S slave mode timing
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S11
I2S_BCLK cycle time (input)
8 x tSYS
ns
S12
I2S_BCLK pulse width high/low (input)
45%
55%
MCLK period
S13
I2S_FS input setup before I2S_BCLK
10
ns
S14
I2S_FS input hold after I2S_BCLK
3
ns
S15
I2S_BCLK to I2S_TXD/I2S_FS output valid
20
ns
S16
I2S_BCLK to I2S_TXD/I2S_FS output invalid
0
ns
S17
I2S_RXD setup before I2S_BCLK
10
ns
S18
I2S_RXD hold after I2S_BCLK
2
ns
S15
S13
S15
S17
S18
S15
S16
S14
S16
S11
S12
I2S_BCLK (input)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
I2S_RXD
Figure 28. I2S timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 44. TSI electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
VDDTSI
Operating voltage
1.71
3.6
V
CELE
Target electrode capacitance range
1
20
500
pF
fREFmax
Reference oscillator frequency
5.5
TBD
MHz
fELEmax
Electrode oscillator frequency
0.5
TBD
MHz
Table continues on the next page...
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
62
Preliminary
Freescale Semiconductor, Inc.
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