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參數(shù)資料
| 型號： | MK20N512VMD100R |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144 |
| 封裝： | 13 X 13 MM, MAPBGA-144 |
| 文件頁數(shù)： | 13/74頁 |
| 文件大小： | 1849K |
| 代理商： | MK20N512VMD100R |
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5.2.1 Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
System and core clock
—
100
MHz
fSYS_USB
System and core clock when USB in operation
20
—
MHz
fBUS
Bus clock
—
50
MHz
FB_CLK
FlexBus clock
—
50
MHz
fFLASH
Flash clock
—
25
MHz
VLPR mode
fSYS
System and core clock
—
2
MHz
fBUS
Bus clock
—
2
MHz
FB_CLK
FlexBus clock
—
2
MHz
fFLASH
Flash clock
—
1
MHz
5.2.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, and I2C signals.
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
—
ns
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
16
—
ns
External reset pulse width (digital glitch filter disabled)
TBD
—
Mode select (EZP_CS) hold time after reset
deassertion
2
—
Bus clock
cycles
Port rise and fall time (high drive strength)
Slew disabled
Slew enabled
—
12
36
ns
Port rise and fall time (low drive strength)
Slew disabled
Slew enabled
—
32
36
ns
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75pF load
General
K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
20
Preliminary
Freescale Semiconductor, Inc.
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