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參數(shù)資料
| 型號： | MK20N512VMD100R |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144 |
| 封裝： | 13 X 13 MM, MAPBGA-144 |
| 文件頁數(shù)： | 19/74頁 |
| 文件大小： | 1849K |
| 代理商： | MK20N512VMD100R |
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J14
J13
TCLK
TRST
Figure 8. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG specifications
Table 13. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25°C
—
32.768
—
kHz
fints_t
Internal reference frequency (slow clock) — user
trimmed
31.25
—
39.0625
kHz
Iints
Internal reference (slow clock) current
—
TBD
—
A
tirefsts
Internal reference (slow clock) startup time
—
TBD
4
s
Δfdco_res_t Resolution of trimmed DCO output frequency at
fixed voltage and temperature — using SCTRIM
and SCFTRIM
—
± 0.1
± 0.3
%fdco
Δfdco_res_t Resolution of trimmed DCO output frequency at
fixed voltage and temperature — using SCTRIM
only
—
± 0.2
± 0.5
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
+ 0.5
- 1.0
± 3.5
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 0.5
± TBD
%fdco
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
3.4
—
4
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed
3
—
5
MHz
Table continues on the next page...
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
26
Preliminary
Freescale Semiconductor, Inc.
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