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參數資料
| 型號： | MK2069-04GITR |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, TSSOP-56 |
| 文件頁數： | 21/21頁 |
| 文件大?。?/td> | 410K |
| 代理商： | MK2069-04GITR |
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
VCXO AND SYNTHESIZER
IDT VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
9
MK2069-04
REV J 051310
Setting the RPV, RV, FV and SV Divider Values
in the VCXO PLL
As shown in the loop bandwidth and damping factor
equations on page 6, or by using the filter response software
available from IDT, increasing FV or SV decreases both
bandwidth and damping factor. Many applications require
that SV = 1. In these cases, one way to decrease loop
bandwidth is to increase the value of FV, which is
accompanied by an increase in the value of RPV and/or RV
to maintain the same PLL frequency multiplication ratio.
However, the phase detector frequency, FPD, also needs to
be considered. FPD is equal to the input frequency divided
by the value of the RPV x RV. FPD should be typically at least
20x the loop bandwidth to prevent loop modulation (phase
noise) by the phase detector frequency. The phase detector
jitter tolerance limit (use 0.4UI) and input phase noise
frequency aliasing should be considerations as well.
Example Loop Filter Component Value
Notes:
1) This filter configuration assures a passband ripple compliant with Bellcore GR-1244-CORE to satisfy wander
transfer requirements (<0.2 dB ripple is required) of a network node. It can be used following a system synchronizer
such as the MT9045 to provide clock jitter attenuation while maintaining Stratum 3 compliance. A 155.52 MHz TCLK
output generated with the VCXO PLL configuration will be OC-3 and OC-12 timing jitter compliant.
2) This is a reduced cost and size variant of the above filter, due to the decreased size of CS. It is useful when
GR-1244-CORE compliance is not needed.
3) This configuration is used to generate a DS3 clock of 44.768 MHz at the TCLK output. This configuration is
GR-1244-CORE compliant when used following a system synchronizer.
4) Lowering the phase detector frequency, by increasing the value of the RPV and/or RV dividers and the FV divider,
will lower the loop bandwidth and/or decrease the size of CS for the same damping factor.
Loop Filter Capacitor Type
Loop filters must use specific types of capacitors.
Recommendations for these capacitors can be found at
Input Phase Compensation Circuit
The VCXO PLL includes a special input clock phase
compensation circuit. It is used when changing the phase of
the input clock, which might occur when selecting a new
reference input through the use of an external clock
multiplexer.
The phase compensation circuit allows the VCXO PLL to
quickly lock to the new input clock phase without producing
extra clock cycles or clock wander, assuming the new clock
is at the same frequency.
Input pin CLR controls the phase compensation circuit. CLR
must remain high for normal operation. When used in
Phase
Detector
Frequency
Xtal
Freq
(MHz)
SV
Div
VCLK
(MHz)
FV
Div
RSET
RS
CS
CP
Loop
BW
(-3dB)
Loop
Damp.
Passband
Peaking
Note
8 kHz
19.44
1
19.44
2430 1 M
560 k 1 F 4.7 nF 22 Hz
4.0
0.15dB at 1Hz
1
8 kHz
19.44
1
19.44
2430 1 M
560 k 0.1 F 4.7 nF 27 Hz
1.4
1.2dB at 6Hz
2
8 kHz
22.368
1
22.368 2796 1 M
680 k 1 F 4.7 nF 20 Hz
4.5
0.12dB at 1Hz
3
19.44 MHz
19.44
1
19.44
128
1 M
27 k
1
F
47 nF
25 Hz
0.85
1.8dB at 8Hz
4
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