- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45328 > MK2069-03GITR 160 MHz, OTHER CLOCK GENERATOR, PDSO56 PDF資料下載
參數(shù)資料
| 型號： | MK2069-03GITR |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, TSSOP-56 |
| 文件頁數(shù)： | 6/19頁 |
| 文件大?。?/td> | 339K |
| 代理商： | MK2069-03GITR |
VCXO-Based Clock Translator with High Multiplication
MDS 2069-03
J
14
Revision 030906
Integrated Circuit Systems, Inc. l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l
MK2069-03
Circuit Troubleshooting
1) IF TCLK or VCLK does not lock to ICLK
First check VCLK to ICLK. It is best to display and
trigger the scope with RCLK, especially if a non-integer
VCXO PLL multiplication ratio is used.
If VCLK is not locked to ICLK:
1.1) Ensure the proper ICLK input is selected.
1.2) Check Divider settings.
1.3) Ensure ICLK is within lock range (within about 100
ppm of the nominal input frequency, limited by pull
range of the external crystal). If in doubt, tweak the
ICLK frequency up and down to see if VCLK locks.
1.4) Ensure ICLK jitter is not excessive. If ICLK jitter is
excessive device may not lock. Also see item 2.1
below.
1.5) Clean the PCB. The VCXO PLL loop filter is very
sensitive to board leakage, especially when the VCXO
PLL phase detector frequency is in the low kHz. If
organic solder flux is used (most common today) scrub
the PCB board with detergent and water and then blow
and bake dry. Inorganic solder flux (Rosen core)
requires solvent. See also section 3 below.
2) If There is Excessive Jitter on VCLK or
TCLK
2.1) The problem may be an unstable input reference
clock. An unstable ICLK will not appear to jitter when
ICLK is used as the oscilloscope trigger source. In this
condition, VCLK and TCLK may appear to be unstable
since the jitter from ICLK (the trigger source) has been
removed by the trigger circuit of the scope.
2.2) The instability may be caused by VCXO PLL loop
filter leakage. Refer to item 1.5 above.
2.3) VCLK and TCLK jitter can also be caused by poor
power supply decoupling. Ensure a bulk decoupling
capacitor is in place.
2.4) Ensure that the VCXO PLL loop bandwidth is
sufficiently low. It should be at least 1/20th of the phase
detector frequency.
2.5) Ensure that the VCXO PLL loop damping is
sufficient. If should be at least 0.7, preferably 1.0 or
higher.
2.6) Ensure that the 2nd pole in the VCXO PLL loop
filter is set sufficiently. In general, CP should be equal to
CS/20. If CP is too high, passband peaking will occur
and loop instability may occur. If CP is set too low,
excessive VCXO modulation by the charge correction
pulses may occur.
3) If There is Excessive Input to Output Skew
3.1) TCLK should track VCLK. The rising edge of TCLK
should be within a few nanoseconds of VCLK.
3.2) VCLK should track RCLK. The rising edge of
VCLK should be within 5-10 nsec of RCLK (VCLK
leads).
3.3) The biggest cause of input to output skew is VCXO
PLL loop filter leakage. Skew is best observed by
comparing ICLK to RCLK. When no leakage is present
the rising edge of RCLK should lag the rising edge of
ICLK by about 10
sec. Loop filter leakage can greatly
increase this lag time or cause the loop to not lock.
Refer to item 1.5, above.
3.4) Another way to view the loop filter leakage is to
observe LDR pin. Use RCLK as the scope trigger. LDR
will produce a negative pulse equal in length to the
charge pump pulse.
3.5) Filter leakage can also be caused by the use of
improper loop capacitors. Refer to the section titled
‘Loop Filter Capacitor Type’ on page 8.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2069-04GITR | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| MK2069-04GI | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| MK20DN512ZVLL10 | RISC MICROCONTROLLER, PQFP100 |
| MK20DN512ZVLQ10 | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144 |
| MK20DX128ZVMD10 | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2069-04 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Universal Clock Translator |
| MK2069-04GI | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2069-04GILF | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2069-04GILFTR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2069-04GITR | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。