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參數(shù)資料
| 型號： | MK2069-03GITR |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, TSSOP-56 |
| 文件頁數(shù)： | 17/19頁 |
| 文件大?。?/td> | 339K |
| 代理商： | MK2069-03GITR |
VCXO-Based Clock Translator with High Multiplication
MDS 2069-03
J
7
Revision 030906
Integrated Circuit Systems, Inc. l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l
MK2069-03
CP establishes a second pole in the VCXO PLL loop
filter. For higher damping factors (> 1), calculate the
value of CP based on a CS value that would be used for
a damping factor of 1. This will minimize baseband
peaking and loop instability that can lead to output jitter.
CP also dampens VCXO input voltage modulation by
the charge pump correction pulses. A CP value that is
too low will result in increased output phase noise at
the phase detector frequency due to this. In extreme
cases where input jitter is high, charge pump current is
high, and CP is too small, the VCXO input voltage can
hit the supply or ground rail resulting in non-linear loop
response.
The best way to set the value of CP is to use the filter
response software available from ICS (please refer to
the following section). CP should be increased in value
until it just starts affecting the passband peak.
Loop Filter Response Software
Online tools to calculate loop filter response can be
found at www.icst.com.
Graph of Charge Pump Current vs. Value of RSET (external resistor)
Charge Pump Current, Example Settings
from Above Graph
Notes on Setting Charge Pump Current
The recommended range for the charge pump current
is 25
A to 300 A. Below 25 A, loop filter charge
leakage, due to PCB or capacitor leakage, can become
a problem. This loop filter leakage can cause locking
problems, output clock cycle slips, or low frequency
phase noise.
As can be seen in the loop bandwidth and damping
factor equations or by using the filter response software
available from ICS, increasing charge pump current
(ICP) increases both bandwidth and damping factor.
10E-6
100E-6
1E-3
100E+3
1E+6
10E+6
RSET, ohms
I CP
,A
m
ps
Recommended Range
of Operation
RSET
Charge Pump Current
(ICP)
5 M
25
A
3 M
42
A
2 M
65
A
1 M
125
A
480 k
255
A
400 k
300
A
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MK2069-04 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Universal Clock Translator |
| MK2069-04GI | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MK2069-04GILF | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2069-04GILFTR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2069-04GITR | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
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