參數(shù)資料
型號(hào): MK2069-03GITR
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 160 MHz, OTHER CLOCK GENERATOR, PDSO56
封裝: 6.10 MM, 0.50 MM PITCH, TSSOP-56
文件頁數(shù): 1/20頁
文件大?。?/td> 204K
代理商: MK2069-03GITR
DATASHEET
VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION
MK2069-03
IDT / ICS VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION 1
MK2069-03
REV J 030906
Description
The MK2069-03 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that offers system
synchronization, jitter attenuation and frequency
translation. It can accept an input clock over a wide range of
frequencies and produces a de-jittered, low phase noise
clock output. The device is optimized for user configuration
by providing access to all major PLL divider functions. No
power-up programming is needed as configuration is pin
selected. External VCXO loop filter components provide an
additional level of performance tailoring.
The MK2069-03 features a very wide range VCXO PLL
feedback divider, allowing high frequency multiplication
ratios and therefore the input of very low input reference
frequencies. The lock detector (LD) output serves as a
clock status monitor. The clear (CLR) input enables rapid
synchronization to the phase of a newly selected input
clock, while eliminating the generation of extra clock cycles
and wander caused by memory in the PLL feedback divider.
CLR also serves as a temporary holdover function when
kept low.
Features
Wide range VCXO PLL feedback divider allows high
frequency multiplication ratios and the input of very low
input reference frequencies
Input clock frequency of <1kHz to 13.5MHz
Output clock frequency of 500kHz to 160MHz
PLL lock status output
VCXO-based clock generation offers very low jitter and
phase noise generation, even with low frequency or jittery
input clock.
PLL Clear function (CLR input) allows the VCXO to
free-run, offering a short term holdover function.
2nd PLL provides frequency translation of VCXO PLL to
higher or alternate output frequencies.
Device will free-run in the absence of an input clock (or
stopped input clock) based on the VCXO frequency
pulled to minimum frequency limit.
Low power CMOS technology
56 pin TSSOP package
Single 3.3V power supply
Block Diagram
C harge
Pum p
VC XO
P u lla b le
xtal
VC LK
X2
X1
IS E T
4
VD D
4
CL R
LF
FV D iv ide r
1 to 4096
SV
Div id e r
1,2,4 ,6,8,
10,12,16
IC L K
RT
Div id e r
1 to 4
P hase
Detector
VC XO
PLL
FT D iv ider
1 to 64
ST
Div id e r
2,4,8,16
VC O
T ra n slato r
PLL
SV 2 :0
3
FV 1 1 :0
FT 5 :0
6
ST 1 :0
2
TC LK
OE V
OE T
LD
OE L
GN D
RCL K
OE R
L o ck D e tecto r
12
LD C
LD R
LFR
RT 1 :0
2
FPV D iv ide r
2 to 65
F PV5 :0
6
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