參數(shù)資料
型號(hào)： MK2069-02GITR
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： 160 MHz, OTHER CLOCK GENERATOR, PDSO56
封裝： 6.10 MM, 0.50 MM PITCH, TSSOP-56
文件頁(yè)數(shù)： 20/20頁(yè)
文件大?。?/td> 347K
代理商： MK2069-02GITR
VCXO-Based Clock Jitter Attenuator and Translator
MDS 2069-02 G
9
Revision 050203
Integrated Circuit Systems, Inc. l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l
MK2069-02
Example Loop Filter Component Values
Notes:
1) The above examples illustrate the ability to adjust the VCXO PLL loop bandwidth by changing the PV
Divider setting only. Settings of the Translator PLL do not affect the VCXO PLL loop bandwidth, so a TCLK
output frequency of 77.76 MHz or 155.52 MHz could be present, for example, with any of the above
configurations. A VCXO gain (Kvco) of 4200 MHz/V was used for all bandwidth calculations.
2) The top group of settings use a minimal sized loop filter capacitor CS which minimizes cost and board
space.
3) The middle group of settings use a larger sized loop filter capacitor CP allowing a lower PV Divider setting
for similar bandwidth and damping performance. This provides a higher phase detector frequency (equal to
the RCLK frequency, as shown) which is needed in applications subject to higher frequency reference clock
jitter to avoid jitter aliasing. Note that a higher phase detector frequency reduces jitter tolerance as well.
4) The bottom group of settings also use a larger sized loop filter capacitor CS, but an increased PV Divider
setting to achieve higher damping factors. A damping factor of 4 or higher is required to assure a passband
ripple of <0.2 dB which is required to comply with the Bellcore GR-1244-CORE wander transfer limit. The
value of CP also must not be excessive.
5) This setting would be a good choice for many 19.44 MHz jitter attenuation applications. It could be used,
for example, when following a system synchronizer such as the MT9045 to provide clock jitter attenuation
while maintaining Stratum 3 compliance. A 155.52 MHz TCLK output generated with this VCXO PLL
configuration will be OC-3 and OC-12 timing jitter compliant. The 80 Hz bandwidth is high enough to allow the
MT9045 jitter transfer characteristics to dominate, yet low enough to provide good jitter attenuation. The
passband peak occurs past the MT9045 frequency roll-off point, further protecting against excessive wander
transfer gain. This higher loop bandwidth also provides improved stability of the VCXO circuit.
Input
(ICLK)
Frequency
Xtal
Freq
(MHz)
VCLK
(MHz)
RCLK
(MHz)
PV
Div
FV
Div
SV
Div
RSET
RS
CS
CP
Loop
BW
(-3dB)
Loop
Damp.
Passband
Peaking
Notes
19.44 MHz
19.44
0.008 2430
11
1 M
560 k 0.1 F1 nF
24 Hz
1.3
1 dB at 5Hz
2
19.44 MHz
19.44
19.44 0.0162 1200
11
1 M
560 k 0.1 F1 nF
48 Hz
1.9
0.5 dB at 7Hz
2
19.44 MHz
19.44
19.44 0.0324 600
11
1 M
560 k 0.1 F1 nF 110 Hz
2.6
0.3 dB at 10Hz
2
19.44 MHz
19.44
19.44 0.6075
32
11
2 M
22 k
1
F
22 nF
38 Hz
1
1.5 dB at 11Hz
3
19.44 MHz
19.44
1.215
16
11
2 M
22 k
1
F
22 nF
70 Hz
1.4
0.75dB at 13Hz
3
19.44 MHz
19.44
9.72
2
11
2 M
22 k
1
F
22 nF 550 Hz
4
0.15dB at 30Hz
3
19.44 MHz
19.44
19.44 0.0648 300
11
2 M
168 k 1 F
4.7 nF
30 Hz
2.5
0.3dB at 3Hz
4
19.44 MHz
19.44
0.162
120
11
2 M
168 k 1 F
4.7 nF
80 Hz
4
0.15dB at 5Hz
4,5
19.44 MHz
19.44
0.249
78
11
2 M
168 k 1 F
4.7 nF 140 Hz
5
0.15dB at 10Hz
4
相關(guān)PDF資料
PDF描述
MK2069-02GILFTR 160 MHz, OTHER CLOCK GENERATOR, PDSO56
MK2069-02GILFTR 160 MHz, OTHER CLOCK GENERATOR, PDSO56
MK2069-03GITR 160 MHz, OTHER CLOCK GENERATOR, PDSO56
MK2069-03GITR 160 MHz, OTHER CLOCK GENERATOR, PDSO56
MK2069-04GITR 160 MHz, OTHER CLOCK GENERATOR, PDSO56
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