參數(shù)資料
型號(hào)： MK2069-02GITR
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 160 MHz, OTHER CLOCK GENERATOR, PDSO56
封裝： 6.10 MM, 0.50 MM PITCH, TSSOP-56
文件頁(yè)數(shù)： 14/20頁(yè)
文件大?。?/td> 347K
代理商： MK2069-02GITR
VCXO-Based Clock Jitter Attenuator and Translator
MDS 2069-02 G
3
Revision 050203
Integrated Circuit Systems, Inc. l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l
MK2069-02
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
PV5
Input
Phase Detector Divider bit 5, VCXO PLL, internal pull-up.
2
PV6
Input
Phase Detector Divider bit 6, VCXO PLL, internal pull-up.
3
PV7
Input
Phase Detector Divider bit 7, VCXO PLL, internal pull-up.
4
PV8
Input
Phase Detector Divider bit 8, VCXO PLL, internal pull-up.
5
FT0
Input
Feedback Divider bit 0 input, Translator PLL, internal pull-up.
6
FT1
Input
Feedback Divider bit 1 input, Translator PLL, internal pull-up.
7
FT2
Input
Feedback Divider bit 2 input, Translator PLL, internal pull-up.
8
PV9
Input
Phase Detector Divider bit 9, VCXO PLL, internal pull-up.
9
PV10
Input
Phase Detector Divider bit 10, VCXO PLL, internal pull-up.
10
PV11
Input
Phase Detector Divider bit 11, VCXO PLL, internal pull-up.
11
ST
Input
Scaling Divider selection bit, Translator PLL, internal pull-up.
12
VDDT
Power
Power Supply connection for translator PLL.
13
GNDT
Ground
Ground connection for translator PLL.
14
X1
-
Crystal oscillator input. Connect this pin to the external reference crystal.
15
VDDV
Power
Power Supply connection for VCXO PLL.
16
X2
-
Crystal oscillator output. Connect this pin to the external reference crystal.
17
GNDV
Ground
Ground connection for VCXO PLL.
18
LFR
-
Loop filter connection, reference node. Refer to loop filter circuit on page 6.
19
LF
-
Loop filter connection, active node. Refer to loop filter circuit on page 6.
20
ISET
-
Charge pump current setting pin. Refer to loop filter circuit on page 6.
21
FV0
Input
Feedback Divider bit 0 input, VCXO PLL, internal pull-up.
22
FV1
Input
Feedback Divider bit 1input, VCXO PLL, internal pull-up.
23
FV2
Input
Feedback Divider bit 2 input, VCXO PLL, internal pull-up.
24
FV3
Input
Feedback Divider bit 3 input, VCXO PLL, internal pull-up.
25
FV4
Input
Feedback Divider bit 4 input, VCXO PLL, internal pull-up.
26
FV5
Input
Feedback Divider bit 5 input, VCXO PLL, internal pull-up.
27
FV6
Input
Feedback Divider bit 6 input, VCXO PLL, internal pull-up.
28
FV7
Input
Feedback Divider bit 7 input, VCXO PLL, internal pull-up.
29
FV8
Input
Feedback Divider bit 8 input, VCXO PLL, internal pull-up.
30
FV9
Input
Feedback Divider bit 9 input, VCXO PLL, internal pull-up.
31
FV10
Input
Feedback Divider bit 10 input, VCXO PLL, internal pull-up.
32
FV11
Input
Feedback Divider bit 11 input, VCXO PLL, internal pull-up.
33
PV0
Input
Phase Detector Divider bit 0, VCXO PLL, internal pull-up.
34
PV1
Input
Phase Detector Divider bit 1, VCXO PLL, internal pull-up.
35
ICLK
Input
Reference clock input, 5V tolerant input.
36
CLR
Input
Clear input, allows VCXO to free-run when low, internal pull-up.
37
LDC
-
Lock detector threshold setting circuit connection. Refer to circuit on page 10.
38
GND
Ground
Digital ground connection.
39
LDR
Power
Lock detector threshold setting circuit connection. Refer to circuit on page 10.
40
RCLK
Output
Reference Clock output, pre-divided phase detector feedback clock.
41
GNDP
Ground
Ground connection for output drivers (VCLK, TCLK, RCLK, LD, LDR).
相關(guān)PDF資料
PDF描述
MK2069-02GILFTR 160 MHz, OTHER CLOCK GENERATOR, PDSO56
MK2069-02GILFTR 160 MHz, OTHER CLOCK GENERATOR, PDSO56
MK2069-03GITR 160 MHz, OTHER CLOCK GENERATOR, PDSO56
MK2069-03GITR 160 MHz, OTHER CLOCK GENERATOR, PDSO56
MK2069-04GITR 160 MHz, OTHER CLOCK GENERATOR, PDSO56
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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