參數(shù)資料
型號(hào): MK2069-02GILFTR
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 160 MHz, OTHER CLOCK GENERATOR, PDSO56
封裝: 6.10 MM, 0.50 MM PITCH, TSSOP-56
文件頁數(shù): 10/20頁
文件大?。?/td> 347K
代理商: MK2069-02GILFTR
VCXO-Based Clock Jitter Attenuator and Translator
MDS 2069-02 G
18
Revision 050203
Integrated Circuit Systems, Inc. l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l
MK2069-02
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85
° C
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Crystal Frequency Range
(Note 1)
fXTAL
Using recommended
crystal
13.5
27
MHz
VCXO Crystal Pull Range
fXP
Using recommended
crystal
±115
±150
ppm
VCXO Crystal Free-Run
Frequency (Note 2)
fXF
Input reference = 0 Hz
-300
-150
ppm
Input Clock Frequency (Note 3)
fI
0.002
27
MHz
Input Clock Pulse Width
tID
Positive or Negative
Pulse
10
nsec
VCXO PLL Phase Detector
Frequency
fPD
0.001
27
MHz
Phase Detector Jitter Tolerance
tJT
1 UI = phase detector
period
0.4
UI
Timing Jitter, Filtered
500Hz-1.3MHz (OC-3)
tOJf
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
95
ps
Timing Jitter, Filtered
65kHz-5MHz (OC-3)
tOJf
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
85
ps
Timing Jitter, Filtered
1kHz-5MHz (OC-12)
tOJf
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
105
ps
Timing Jitter, Filtered
250kHz-5MHz (OC-12)
tOJf
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
80
ps
Output Frequency
VCO frequency = 40 to
320 MHz
2.5
160
MHz
Output Duty Cycle (% high time),
VCLK when SV Divider = 1
tOD
Measured at VDD/2,
CL=15pF
40
50
60
%
Output Duty Cycle (% high time),
VCLK when SV Divider > 1,
TCLK
tOD
Measured at VDD/2,
CL=15pF
44
50
65
%
Output High Time, RCLK
(Note 4)
tOH
Measured at VDD/2,
CL=15pF
0.5
VCLK
Period
Output Rise Time, VCLK and
RCLK
tOR
0.8 to 2.0V, CL=15pF
1.5
2
ns
相關(guān)PDF資料
PDF描述
MK2069-02GILFTR 160 MHz, OTHER CLOCK GENERATOR, PDSO56
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