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參數(shù)資料
| 型號(hào)： | MK2049-11SITR |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 166K |
| 代理商： | MK2049-11SITR |
Communications Clock PLL
MDS 2049-11 C
4
Revision 021402
Integrated Circuit Systems, Inc. q 525 Race Street San Jose, CA 95126 q tel (408) 295-9800 q
www.icst.com
MK2049-11
Functional Description
The MK2049-11 is a PLL (Phased Locked Loop) based
clock generator that generates output clocks
synchronized to an input reference clock. It contains
two cascaded PLL’s with table selected divider ratios.
The first PLL is VCXO-based and uses an external
pullable crystal as part of the normal “VCO” (voltage
controlled oscillator) function of the PLL. The use of a
VCXO assures a low phase noise clock source even
when a low PLL loop bandwidth is implemented. A low
loop bandwidth is needed when the input reference
frequency at the phase detector is low, or when jitter
attenuation of the input reference is desired.
The second PLL is used to translate or multiply the
frequency of the VCXO PLL. The Translator PLL uses
an on-chip VCO for output clock generation and is
configured with high loop bandwidth.
The divide values of the divider blocks within both PLLs
are set through table selection.
External components are used to configure the VCXO
PLL loop response. This serves to maximize loop
stability and to achieve the desired input clock jitter
attenuation characteristics.
Application Information
The MK2049-11 is a mixed analog / digital integrated
circuit that is sensitive to PCB (printed circuit board)
layout and external component selection. Used
properly, the device will provide the same high
performance expected from a canned VCXO-based
hybrid timing device, but at a lower cost. To help avoid
unexpected problems, the guidance provided in the
sections below should be followed.
Setting the VCXO PLL Loop Response.
The VCXO PLL loop response is determined both by
fixed device characteristics and by other characteristics
set by the user. This includes the values of RZ, C1, and
C2 as shown in the Block Diagram on page 1.
The VCXO PLL loop bandwidth is approximated by:
Where:
RZ = Value of resistor RZ in loop filter in Ohms
ICP = Charge pump current in amps = 50 A
(fixed, not adjustable)
KO = VCXO Gain in Hz/V
(see table on page 8)
N = XTAL frequency / input clock frequency
(see 4th column of table on page 6)
The above equation calculates the “normalized” loop
bandwidth (denoted as “NBW”) which is approximately
equal to the - 3dB bandwidth. NBW does not take into
account the effects of damping factor or the second
pole imposed by C2. It does, however, provide a useful
approximation of filter performance.
To prevent jitter on the output clocks due to modulation
of the VCXO PLL by the phase detector frequency, the
following general rule should be observed:
.
The PLL loop damping factor is determined by:
Where:
C1 = Value of capacitor C1 in loop filter in
Farads
In general, the loop damping factor should be 0.7 or
greater to ensure output stability. A higher damping
factor will create less peaking in the passband and will
further assure output stability with the presence of
system and power supply noise. A damping factor of 4
or greater will assure a passband peak less then 0.2dB
NBW(VCXO PLL)
R
Z
I
CP
×
K
O
×
2
π N
×
----------------------------------
=
NBW(VCXO PLL)
f(Input Frequency)
20
----------------------------------------
≤
DF(VCLK)
R
Z
2
------
I
CP
C
1
×
K
O
×
N
---------------------------------
×
=
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| MK2049-11SITRLF | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
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| MK2049-11SI | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-45ASI | 125 MHz, OTHER CLOCK GENERATOR, PDSO20 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-34 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-34A | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 Volt Communications Clock VCXO PLL |
| MK2049-34SAI | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2049-34SAILF | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK2049-34SAILFTR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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