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參數(shù)資料
| 型號(hào)： | MK2049-11SITR |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁(yè)數(shù)： | 13/13頁(yè) |
| 文件大?。?/td> | 166K |
| 代理商： | MK2049-11SITR |
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Communications Clock PLL
MDS 2049-11 C
9
Revision 021402
Integrated Circuit Systems, Inc. q 525 Race Street San Jose, CA 95126 q tel (408) 295-9800 q
www.icst.com
MK2049-11
The concept behind the crystal load capacitors is
introduced on page 7. To determine the need for and
value of these capacitors, you will need a PC board of
your final layout, a frequency counter capable of less
than 1 ppm resolution and accuracy, two power
supplies, and some samples of the crystals which you
plan to use in production, along with measured initial
accuracy for each crystal at the specified crystal load
capacitance, CL.
To determine the value of the crystal capacitors:
1. Connect VDD of the MK2049-11 to 5V. Connect pin 5
to the second power supply. Adjust the voltage on pin 5
to 0V. Measure and record the frequency of the CLK
output.
2. Adjust the voltage on pin 5 to 5V. Measure and
record the frequency of the same output.
To calculate the centering error:
Where:
ftarget = nominal crystal frequency
errorxtal =actual initial accuracy (in ppm) of the crystal
being measured
If the centering error is less than ±15 ppm, no
adjustment is needed. If the centering error is more
than 15 ppm negative, the PC board has too much
stray capacitance and will need to be redone with a
new layout to reduce stray capacitance. (The crystal
may be re-specified to a lower load capacitance
instead. Contact ICS MicroClock for details.) If the
centering error is more than 15 ppm positive, add
identical fixed centering capacitors from each crystal
pin to ground. The value for each of these caps (in pF)
is given by:
External Capacitor =
2 x (centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied
by your crystal vendor. If you do not know the value,
assume it is 30 ppm/pF. After any changes, repeat the
measurement to verify that the remaining error is
acceptably low (less than ±15ppm).
Circuit Troubleshooting
1) IF CLK1 or CLK2 does not lock to ICLK
First check for locking between ICLK and the 8k output.
If locking does not occur:
1.1) Ensure the table selection is made and that the
proper crystal frequency is in use.
1.2) Ensure ICLK is within lock range (within about 100
ppm of the nominal input frequency, limited by pull
range of the external crystal). If in doubt, tweak the
ICLK frequency up and down to see if the 8k output
locks.
1.3) Ensure ICLK jitter is not excessive. If ICLK jitter is
excessive device may not lock. Also see item 2.1
below.
1.4) Clean the PCB. The VCXO PLL loop filter is very
sensitive to board leakage, especially when the VCXO
PLL phase detector frequency is in the low kHz range.
If organic solder flux is used (most common today)
scrub the PCB board with detergent and water and
then blow and bake dry. Inorganic solder flux (Rosen
core) requires solvent. See also section 2 below.
2) If There is Excessive Jitter on the 8k output,
or CLK1 and CLK2 outputs
2.1) The problem may be an unstable input reference
clock. An unstable ICLK will not appear to jitter when
ICLK is used as the oscilloscope trigger source. In this
condition, the device clock outputs may appear to be
unstable since the jitter from ICLK (the trigger source)
has been removed by the trigger circuit of the scope.
2.2) The instability may be caused by VCXO PLL loop
filter leakage. Refer to item 1.4 above.
2.3) Output clock jitter can also be caused by poor
power supply decoupling. Ensure a bulk decoupling
capacitor is in place.
2.4) Ensure that the VCXO PLL loop damping is
sufficient. It should be at least 0.7, preferably 1.0 or
higher.
2.5) Ensure that the 2nd pole in the VCXO PLL loop
filter is set sufficiently. In general, C2 should be equal to
C1/20. If C2 is too high, passband peaking will occur
and loop instability may occur. If C2 is set too low,
excessive VCXO modulation by the charge correction
pulses may occur.
Error
10
6
x
f
5V
f
tet
arg
–
()
f
0V
f
tet
arg
–
()
+
2
f
tet
arg
×
--------------------------------------------------------------------------
error
xtal
–
=
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-34 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-34A | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 Volt Communications Clock VCXO PLL |
| MK2049-34SAI | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2049-34SAILF | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK2049-34SAILFTR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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