參數(shù)資料
型號(hào)： MIP7965-750MR
元件分類(lèi)： 微控制器/微處理器
英文描述： 64-BIT, 750 MHz, MICROPROCESSOR, PQFP216
封裝： 26 X 26 MM, LEAD FREE, PLASTIC PACKAGE-216
文件頁(yè)數(shù)： 16/20頁(yè)
文件大?。?/td> 828K
代理商： MIP7965-750MR
5
SCD7965 Rev A Preliminary 11/16/05
Aeroflex Plainview
Clock/Control Interface
PIN NAME
TYPE
DESCRIPTION
SysClock
Input
System clock
Master clock input used as the system interface reference clock. All output timings are relative
to this input clock. Pipeline operation frequency is derived by multiplying this clock up by the
factor selected during boot initialization.
Power Supply
PIN NAME
TYPE
DESCRIPTION
VccInt
Input
Power supply for core.
VccIO
Input
Power supply for I/O.
VccP
Input
Vcc for PLL
Quiet VccInt for the internal phase locked loop. Must be connected to VccInt through a filter
circuit.
VccJ
Input
Power supply used for JTAG.
Vss
Input
Ground Return.
VssP
Input
Vss for PLL
Quiet Vss for the internal phase locked loop. Must be connected to Vss through a filter circuit.
Interrupt Interface
PIN NAME
TYPE
DESCRIPTION
INT[9:0]*
Input
Interrupt
Ten general processor interrupts, bit-wise ORed with bits 9:0 of the interrupt register.
NMI*
Input
Non-maskable interrupt
Non-maskable interrupt, ORed with bit 15 of the interrupt register..
JTAG Interface
PIN NAME
TYPE
DESCRIPTION
JTDI/DBDI
Input
JTAG/EJTAG data in
JTAG/EJTAG serial data in.
JTCK/DBCK
Input
JTAG/EJTAG clock input
JTAG/EJTAG serial clock input.
JTDO/DBDO
Output
JTAG/EJTAG data out
JTAG/EJTAG serial data out.
JTMS/DBMS
Input
JTAG/EJTAG command
JTAG/EJTAG command signal, signals that the incoming serial data is command data.
JTRST*/DBRST*
Input
JTAG/EJTAG reset.
JTAGSEL
Input
JTAG/EJTAG select Selects
JTAG when JTAGSEL=1 ; selects EJTAG when JTAGSEL=0
相關(guān)PDF資料
PDF描述
MIP7965-750F17T 64-BIT, 750 MHz, MICROPROCESSOR, CQFP208
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