參數(shù)資料
型號: MICRF213AYQS
廠商: MICREL INC
元件分類: 消費家電
英文描述: 1.8 V dual UART, 20 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface, SOT912-1 (TFBGA36), Tray Pack, Bakeable, Multiple
中文描述: SPECIALTY CONSUMER CIRCUIT, PDSO16
封裝: QSOP-16
文件頁數(shù): 4/16頁
文件大?。?/td> 850K
代理商: MICRF213AYQS
Micrel, Inc.
MICRF213
Symbol
May 2007
4
M9999-052307-A
(408) 944-0800
Parameter
Condition
Min
Typ
Max
Units
Demodulator
CTH Source Impedance
F
REFOSC
= 9.81563MHz
165
k
CTH Leakage Current
T
A
= 25oC
T
A
= +105oC
SEL0=0, SEL1=0
SEL0=1, SEL1=0
SEL0=0, SEL1=1
±2
±800
1180
2360
4720
nA
nA
Demodulator Filter
Bandwidth @ 315MHz
(Programmable, see
application section)
SEL0=1, SEL1=1
9400
Hz
Digital / Control Functions
DO pin output current
As output
CI = 15pF, pin DO, 10-90%
source @ 0.8Vdd
sink @ 0.2Vdd
260
600
2
μA
Output rise and fall times
μsec
RSSI
RSSI DC Output Voltage
Range
RSSI response slope
-110dBm to -50dBm
0.4 – 1.9
V
-110dBm to -50dBm
25
mV/dB
RSSI Output Current
400
μA
RSSI Output Impedance
RSSI Response Time
±15
50% data duty cycle, input power to Antenna = -
20 dBm
200
0.3
Sec
Notes:
1.
2.
3.
Exceeding the absolute maximum rating may damage the device.
The device is not guaranteed to function outside of its operating rating.
Device is ESD sensitive. Use appropriate ESD precautions. Exceeding the absolute maximum rating may damage the device.
Sensitivity is defined as the average signal level measured at the input necessary to achieve 10-2 BER (bit error rate). The input signal is
defined as a return-to-zero (RZ) waveform with 50% average duty cycle (Manchester encoded) at a data rate of 1kbps.
When data burst does not contain preamble, duty cycle is defined as total duty cycle, including any “quiet” time between data bursts. When
data bursts contain preamble sufficient to charge the slice level on capacitor C , then duty cycle is the effective duty cycle of the burst alone.
[For example, 100msec burst with 50% duty cycle, and 100msec “quiet” time between bursts. If burst includes preamble, duty cycle is
Ton/(Ton+Toff) = 50%; without preamble, duty cycle is Ton/(Ton+ Toff + Tquiet) = 50msec/(200msec)=25%. Ton is the (Average number of
1’s/burst) x bit time, and Toff = Tburst -Ton.)
4.
5.
TH
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