參數(shù)資料
型號: MICRF213AYQS
廠商: MICREL INC
元件分類: 消費家電
英文描述: 1.8 V dual UART, 20 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface, SOT912-1 (TFBGA36), Tray Pack, Bakeable, Multiple
中文描述: SPECIALTY CONSUMER CIRCUIT, PDSO16
封裝: QSOP-16
文件頁數(shù): 10/16頁
文件大?。?/td> 850K
代理商: MICRF213AYQS
Micrel, Inc.
MICRF213
the top layer close to the REFOSC pins RO1 and
RO2. When care is not taken in the layout, and
crystals from other vendors are used, the oscillator
may take longer times to start as well as the time to
good data in the DO pin to show up. In some cases, if
the stray capacitance is too high (>20pF), the
oscillator may not start at all.
The crystal frequency is calculated by REFOSC = RF
Carrier/(32+(1.1/12)). The local oscillator is low side
injection (32 × 9.81563MHz = 314.1MHz), that is, its
frequency is below the RF carrier frequency and the
image frequency is below the LO frequency. Refer to
Figure 6. The product of the incoming RF signal and
local oscillator signal will yield the IF frequency, which
will then be demodulated by the detector of the
device.
May 2007
10
M9999-052307-A
(408) 944-0800
f
LO
f (MHz)
Image
Frequency
Desired
Signal
Figure 6. Low Side Injection Local Oscillator
REFOSC
(MHz)
9.467411
9.81563
10.75045
Carrier
(MHz)
303.825
315
345.0
HIB Part Number
SA-9.467411-F-10-H-30-30-X
SA-9.815630-F-10-H-30-30-X
SA-10.750450-F-10-H-30-30-X
Table 5. Crystal Frequency and Vendor Part Number
JP1 and JP2 are the bandwidth selection for the
demodulator bandwidth. To set it correctly, it is
necessary to know the shortest pulse width of the
encoded data sent in the transmitter. Reference the
example of the data profile, in the Figure 7, below:
Figure 7. Example of a Data Profile
PW2 is shorter than PW1, so PW2 should be used for
the
demodulator
bandwidth
calculation is found by 0.65/shortest pulse width. After
this value is found, the setting should be done
calculation.
The
according to Table 6. For example, if the pulse period
is 140μsec, 50% duty cycle, then the pulse width will
be 70μsec (PW = (140 μsec * 50%) / 100). So, a
bandwidth of 9.286kHz would be necessary (0.65 /
70μsec). However, if this data stream had a pulse
period with a 20% duty cycle, then the bandwidth
required would be 23.2kHz (0.65 / 28μsec), which
exceeds the maximum bandwidth of the demodulator
circuit. If one tries to exceed the maximum bandwidth,
the pulse would appear stretched or wider.
SEL0
JP1
SEL1
JP2
Demod.
BW
(hertz)
Shortest
Pulse
(usec)
Maximum
baud rate for
50% Duty
Cycle (hertz)
908
1815
3631
7230
Short
Open
Short
Open
Short
Short
Open
Open
1180
2360
4720
9400
551
275
138
69
Table 6. JP1 and JP2 Setting, 315MHz
Capacitors C6 and C4, Cth and Cagc capacitors
respectively, provide the time base reference for the
data pattern received. These capacitors are selected
according to data profile, pulse duty cycle, dead time
between two received data packets and if the data
pattern has or not a preamble. See Figure 7 for an
example of a data profile.
Other frequencies will have different demodulator
bandwidth limits, which are derived from the reference
oscillator frequency. Table 7 and Table 8, below,
show the limits for the other two most used
frequencies.
SEL0
JP1
SEL1
JP2
Demod.
BW
(hertz)
Shortest
Pulse
(usec)
Maximum
baud rate for
50% Duty
Cycle (hertz)
8770
1754
3500
7000
Short
Open
Short
Open
Short
Short
Open
Open
1140
2280
4550
9100
570
285
143
71
Table 7. JP1 and JP2 Setting, 303.825MHz
SEL0
JP1
SEL1
JP2
Demod.
BW
(hertz)
Shortest
Pulse
(usec)
Maximum
baud rate for
50% Duty
Cycle (Hertz)
992
1985
3977
7954
Short
Open
Short
Open
Short
Short
Open
Open
1290
2580
5170
10340
504
252
126
63
Table 8. JP1 and JP2 Setting, 345.0MHz
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