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參數(shù)資料
| 型號： | MIC2585-2MBTS TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 16/28頁 |
| 文件大小： | 273K |
| 描述： | IC CTRLR HOT SWAP DUAL 24-TSSOP |
| 標準包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 1 V ~ 13.2 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MIC2585-2MBTSTR MIC2585-2MBTSTR-ND |
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MIC2584/2585
Micrel
MIC2584/2585
16
March 2005
and the resulting t
OCSLOW
needed to achieve a 12V output is
approximately 2.5ms. (See "Power-On Reset, Overcurrent
Timer, and Sequenced Output Delays" section to calculate
t
OCSLOW
).
GATE Capacitance Dominated Start-Up
In this case, the value of the load capacitance relative to the
GATE capacitance is small enough such that during start-up
the output current never exceeds the current limit threshold
as determined by Equation 3. The minimum value of C
GATE
that will ensure that the current limit is never exceeded is
given by the equation below:
C
(Min)
I
I
C
GATE
GATE
LIMIT
LOAD
=
?/DIV>
Where C
GATE
is the summation of the MOSFET input capaci-
tance (C
ISS
) specification and the value of the capacitor
connected to the GATE pin of the MIC2584/85 (and MOSFET)
to ground. Once C
GATE
is determined, use the following
equation to determine the output slew rate
dV
OUT
/dt for gate capacitance dominated start-up:
dV /dt
I
C
OUT
GATE
GATE
=
Table 1 depicts the output slew rate for various values of C
GATE
.
I
GATE
= 14?/SPAN>A
C
GATE
dV
OUT
/dt
0.001礔
14V/ms
0.01礔
1.4V/ms
0.1礔
0.14V/ms
1礔
0.014V/ms
Table 1. Output Slew Rate Selection for GATE
Capacitance Dominated Start-Up
Current Limiting and Dual-Level Circuit Breaker
Many applications will require that the inrush and steady state
supply current be limited at a specific value in order to protect
critical components within the system. Connecting a sense
resistor between the VCC and SENSE pins of each channel
sets the nominal current limit value for each channel of the
MIC2584/85 and the current limit is calculated using
Equation 2.
The MIC2584/85 also features a dual-level circuit breaker
triggered via 50mV and 100mV current limit thresholds sensed
across the VCC and SENSE pins. The first level of the circuit
breaker functions as follows. For the MIC2584/85, once the
voltage sensed across these two pins exceeds 50mV on
either channel, the overcurrent timer, its duration set by
capacitor C
FILTER
, starts to ramp the voltage at CFILTER
using a 2.5礎(chǔ) constant current source. If the voltage at
CFILTER reaches the overcurrent timer threshold (V
TMR
) of
1.235V, then CFILTER immediately returns to ground as the
circuit breaker trips and both GATE outputs are immediately
shut down. For the second level, if the voltage sensed across
VCC and SENSE of either channel exceeds 100mV
(J option) at any time, the circuit breaker trips and both
GATE outputs shut down immediately, bypassing the
overcurrent timer period. To disable current limit and circuit
breaker operation, tie each channels SENSE and VCC pins
together and the CFILTER pin to ground.
Output Undervoltage Detection
The MIC2584/85 employ output undervoltage detection by
monitoring the output voltage through a resistive divider
connected at the FB pins. During turn on, while the voltage at
either FB pin is below its threshold (V
FB
), the /POR pin is
asserted low. Once both FB pin voltages cross their respec-
tive threshold (V
FB
), a 2.5礎(chǔ) current source charges capaci-
tor C
POR
. Once the CPOR pin voltage reaches 1.235V, the
time period t
POR
elapses as pin CPOR is pulled to ground and
the /POR pin goes HIGH. If the voltage at either FB drops
below V
FB
for more than 10祍, the /POR pin resets for at least
one timing cycle defined by t
POR
(See "Applications Informa-
tion" for an example).
Input/Output Overvoltage Protection
The MIC2585 monitors and detects overvoltage conditions in
the event of excessive supply transients at the MIC2585
input(s)/output(s). Whenever the voltage threshold is ex-
ceeded at either OV1 or OV2 of the MIC2585, the circuit
breaker is tripped and both GATE outputs are immediately
brought low.
Power-On Reset, Overcurrent Timer, and Sequenced
Output Delays
The Power-On Reset delay, t
POR
, is the time period for the
/POR pin to go HIGH once the lagging voltage exceeds the
power-good threshold (V
FB
) monitored at the FB pin. A
capacitor connected to CPOR sets the interval and is deter-
mined by using Equation 1 with V
POR
substituted for V
START
.
The resulting equation becomes:
t
C
V
I
0.5 C
F
POR
POR
POR
CPOR
POR
=
?/DIV>
E
?/DIV>
?/DIV>
( )
(7)
where the Power-On Reset threshold (V
POR
) and timer
current (I
CPOR
) are typically 1.235V and 2.5礎(chǔ), respectively.
For the MIC2584/85, a capacitor connected to CFILTER is
used to set the timer which activates the circuit breaker during
overcurrent conditions. When the voltage across either sense
resistor exceeds the slow trip current limit threshold of 50mV,
the overcurrent timer begins to charge for a period, t
OCSLOW
,
determined by C
FILTER
. If t
OCSLOW
elapses, then the circuit
breaker is activated and both GATE outputs are immediately
pulled to ground. The following equation is used to determine
the overcurrent timer period, t
OCSLOW
.
t
C
V
I
0.5 C
( F)
OCSLOW
FILTER
TMR
TMR
FILTER
=
?/DIV>
E
?/DIV>
?/DIV>
(8)
where V
TMR
, the overcurrent timer threshold, is 1.235V and
I
TMR
, the overcurrent timer current, is 2.5礎(chǔ). If no capacitor
for CFILTER is used, then t
OCSLOW
defaults to 20祍.
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