參數(shù)資料
型號: MIC2341-2YTQ
廠商: Micrel Inc
文件頁數(shù): 27/32頁
文件大小: 1277K
描述: IC HOT PLUG CTLR DUAL PCI 48TQFP
標準包裝: 250
類型: 熱交換控制器
應用: 通用型,PCI Express?
內部開關:
電源電壓: 3.3V,12V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應商設備封裝: 48-TQFP(7x7)
包裝: 管件
產(chǎn)品目錄頁面: 1085 (CN2011-ZH PDF)
其它名稱: 576-2995
Micrel, Inc.
MIC2341/2341R
 
 
October 2007 
27
M9999-102507-A
 (408) 944-0800
 
Slot[A/B] Fault Reporting
The MIC2341s /FAULT_MAIN[A/B] open-drain digital
output are activated after power-on-reset and become
asserted when:
The ON[A/B] input signals are asserted, AND
" The   12VIN[A/B]   or   the   3VIN[A/B]   input
voltages is less than its respective ULVO
threshold, OR
" The fast OC circuit breaker[A/B] has tripped,
OR
" The slow OC circuit breaker[A/B] has tripped
AND its corresponding C
FILTER[A/B]
  timeout or
the digital filter delay has expired.
In order to clear the /FAULT_MAIN[A/B] outputs once
asserted   and   to   reset   the   corresponding   circuit
breaker(s), a high-to-low transition is required on the
ON[A/B] input signals. Please see /FAULT_MAIN[A/B]
pin descriptions for additional information.
 
Figure 10. State Diagram for /FAULT_MAIN[A/B] Signals
The MIC2341s /FAULT_AUX[A/B] open-drain digital
outputs are activated after power-on-reset and become
asserted when:
The AUXEN[A/B] input signals are asserted, AND
" The slow VAUX[A/B] OC circuit breaker has
tripped   AND   its   corresponding   C
FILTER[A/B]
 
timeout or the digital filter delay has expired,
OR
" The slow VAUX[A/B] OC circuit breaker has
tripped AND the Slot[A/B] die temperature is
higher than 140癈, OR
" The MIC2341s global die temperature is
higher than 160癈
In order to clear the /FAULT_AUX[A/B] outputs once
asserted and to reset the VAUX[A/B] circuit breaker(s), a
high-to-low transition is required on the AUXEN[A/B]
input   signals.   Please   see   /FAULT_AUX[A/B]   pin
descriptions for additional information.
 
If the /FORCE_ON[A/B] digital inputs are used for
diagnostic     purposes,     the     /FAULT_MAIN[A/B],
/FAULT_AUX[A/B],
 
/PWRGD[A/B],
and
/DLY_PWRGD[A/B] digital outputs are de-asserted once
/FORCE_ON[A/B] inputs are asserted.
 
 
Figure 11. State Diagram for /FAULT_AUX[A/B] Signals
 
 
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