參數(shù)資料
型號: MIC2341-2YTQ
廠商: Micrel Inc
文件頁數(shù): 24/32頁
文件大小: 1277K
描述: IC HOT PLUG CTLR DUAL PCI 48TQFP
標(biāo)準(zhǔn)包裝: 250
類型: 熱交換控制器
應(yīng)用: 通用型,PCI Express?
內(nèi)部開關(guān):
電源電壓: 3.3V,12V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 管件
產(chǎn)品目錄頁面: 1085 (CN2011-ZH PDF)
其它名稱: 576-2995
Micrel, Inc.
MIC2341/2341R
 
 
October 2007 
24
M9999-102507-A
 (408) 944-0800
 
external 10k& resistor to V
STBY
 or a local logic supply.
Each /PWRGD[A/B] output is asserted when a slot has
been enabled and has successfully begun delivering
power to its respective +12V, +3.3V, and VAUX outputs.
The /DLY_PWRGD[A/B] outputs are asserted 164ms
after   its   corresponding   /PWRGD[A/B]   output.   An
equivalent logic diagram for /PWRGD[A/B] is shown in
Figure 8 with their corresponding state diagrams.
 
Figure 8. State Diagrams for /PWRGD[A/B] and
/DLY_PWRGD[A/B]
SYSPWRGD Digital Output
SYSPWRGD is an open-drain, asserted active-HIGH
digital output provided by the MIC2341 for additional slot
status information to the service or system processor.
This output is normally connected by an external 10k&
resistor to V
STBY
  or a local logic supply. There is one
SYSPWRGD output for each MIC2341 and this signal
becomes activated after power-on-reset. This signal is
asserted unless at least one PCIe slot is occupied, either
ON[A/B] and/or AUXEN[A/B] of the slot in question is
asserted,   either   /FORCE_ON[A/B]   inputs   are   not
asserted, and the output voltages at the load are lower
than    respective    Power-is-Good    output    threshold
voltages. Functionality of the SYSPWRGD output signal
has been designed to accommodate single- and dual-
slot applications as well as applications where the
MAIN[A/B] outputs are used, but the VAUX[A/B] outputs
are not. In multiple MIC2341 applications where one or
more PCIe slots are unused and one or multiple ON[A/B]
and AUXEN[A/B] input signals are not asserted, each
SYSPWRGD   digital   output   will   appear   asserted
facilitating an OR-tying of all SYSPWRGD output
signals, thereby ensuring correct logic functionality
across the entire system. See Table 1 for the
SYSPWRGD truth table.
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