269
ATmega64A [DATASHEET]
8160D–AVR–02/2013
Similarly, when reading the Fuse High bits, load 0x0003 in the Z-pointer. When an LPM instruction is executed
within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse High bits
description and mapping of the Fuse High bits.
When reading the Extended Fuse bits, load 0x0002 in the Z-pointer. When an LPM instruction is executed within
three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Extended Fuse bits (EFB)
will be loaded in the destination register as shown below. Refer to
Table 28-3 on page 275 for detailed description
and mapping of the Fuse High bits.
Fuse and Lock bits that are programmed will be read as zero. Fuse and Lock bits that are unprogrammed will be
read as one.
27.8.10
Preventing Flash Corruption
During periods of low V
CC, the Flash program can be corrupted because the supply voltage is too low for the CPU
and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the
same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write
sequence to the Flash requires a minimum voltage to operate correctly. Second, the CPU itself can execute
instructions incorrectly, if the supply voltage for executing instructions is too low.
Flash corruption can easily be avoided by following these design recommendations (one is sufficient):
1.
If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to prevent
any Boot Loader software updates.
2.
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by
enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not,
an external low V
CC Reset Protection circuit can be used. If a reset occurs while a write operation is in prog-
ress, the write operation will be completed provided that the power supply voltage is sufficient.
3.
Keep the AVR core in Power-down Sleep mode during periods of low V
CC. This will prevent the CPU from
attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the
Flash from unintentional writes.
27.8.11
Programming Time for Flash when Using SPM
The calibrated RC Oscillator is used to time Flash accesses.
Table 27-5 shows the typical programming time for
Flash accesses from the CPU.
Bit
765
4
3210
Rd
FLB7
FLB6
FLB5
FLB4
FLB3
FLB2
FLB1
FLB0
Bit
765
4
3210
Rd
FHB7
FHB6
FHB5
FHB4
FHB3
FHB2
FHB1
FHB0
Bit
7
6
5
4
3210
Rd
–
EFB1
EFB0
Table 27-5.
SPM Programming Time
Symbol
Min Programming Time
Max Programming Time
Flash write (Page Erase, Page Write, and
write Lock bits by SPM)
3.7 ms
4.5 ms