119
32000D–04/2011
AVR32
9.3.11
Coprocessor interface
Table 9-13.
Coprocessor Interface
Mnemonics
Operands / Syntax
Description
Operation
Rev
cop
E
CP#, CRd, CRx,
CRy, Op
Coprocessor operation.
CRd
← CRx Op CRy
1
ldc.d
E
CP#, CRd, Rp[disp]
Load coprocessor register
CRd+1:CRd
← *(Rp+ZE(disp8<<2))
1
E
CP#, CRd, --Rp
Load coprocessor register with pre-
decrement
CRd+1:CRd
← *(--Rp)
1
E
CP#, CRd,
Rb[Ri<<sa]
Load coprocessor register with indexed
addressing
CRd+1:CRd
← *(Rb+(Ri << sa2))
1
ldc0.d
E
CRd, Rp[disp]
Load coprocessor 0 register
CRd+1:CRd
← *(Rp+ZE(disp12<<2))
1
ldc.w
E
CP#, CRd, Rp[disp]
Load coprocessor register
CRd
← *(Rp+ZE(disp8<<2))
1
E
CP#, CRd, --Rp
Load coprocessor register with pre-
decrement
CRd
← *(--Rp)
1
E
CP#, CRd,
Rb[Ri<<sa]
Load coprocessor register with indexed
addressing
CRd
← *(Rb+(Ri << sa2))
1
ldc0.w
E
CRd, Rp[disp]
Load coprocessor 0 register
CRd
← *(Rp+ZE(disp12<<2))
1
ldcm.d
E
CP#, Rp{++},
ReglistCPD8
Load multiple coprocessor double
registers
See instruction set reference
1
ldcm.w
E
CP#, Rp{++},
ReglistCPH8
Load multiple coprocessor high
registers
See instruction set reference
1
ldcm.w
E
CP#, Rp{++},
ReglistCPL8
Load multiple coprocessor low registers
See instruction set reference
1
mvcr.d
E
CP#, Rd, CRs
Move from coprocessor to register
Rd+1:Rd
← CRs+1:CRs
1
mvcr.w
E
CP#, Rd, CRs
Move from coprocessor to register
Rd
← CRs
1
mvrc.d
E
CP#, CRd, Rs
Move from register to coprocessor
CRd+1:CRd
← Rs+1:Rs
1
mvrc.w
E
CP#, CRd, Rs
Move from register to coprocessor
CRd
← Rs
1
stc.d
E
CP#, Rp[disp], CRs
Store coprocessor register
*(Rp+ZE(disp8<<2))
← CRs+1:CRs
1
E
CP#, Rp++, CRs
Store coprocessor register with post-
increment
*(Rp--)
← CRs+1:CRs
1
E
CP#, Rb[Ri<<sa],
CRs
Store coprocessor register with indexed
addressing
*(Rb+(Ri << sa2))
← CRs+1:CRs
1
stc0.d
E
Rp[disp], CRs
Store coprocessor 0 register
*(Rp+ZE(disp12<<2))
← CRs+1:CRs
1
stc.w
E
CP#, Rp[disp], CRs
Store coprocessor register
*(Rp+ZE(disp8<<2))
← CRs
1
E
CP#, Rp++, CRs
Store coprocessor register with post-
increment
*(Rp++)
← CRs
1
E
CP#, Rb[Ri<<sa],
CRs
Store coprocessor register with indexed
addressing
*(Rb+(Ri << sa2))
← CRs
1
stc0.d
E
Rp[disp], CRs
Store coprocessor 0 register
*(Rp+ZE(disp12<<2))
← CRs
1