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參數(shù)資料
| 型號： | MCZ33991EG |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Gauge Driver Integrated Circuit |
| 中文描述： | 儀表驅(qū)動集成電路 |
| 文件頁數(shù)： | 18/36頁 |
| 文件大?。?/td> | 481K |
| 代理商： | MCZ33991EG |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
18
33991
TIMING DESCRIPTIONS AND DIAGRAMS
COMMUNICATION MEMORY MAPS
SO COMMUNICATION
When the CS pin is pulled low, the internal status word
register is loaded into the output register and the fault data is
clocked out MSB (OD15) first. Following a CS transition 0 to
1, the device determines if the message shift was of a valid
length and if so, latches the data into the appropriate
registers. A valid message length is one that is greater than
0 bits and a multiple of 16 bits. At this time, the SO pin is tri-
stated and the Fault
Status Register is now able to accept new fault status
information. If the message length was determined to be
invalid, the status information is not cleared. It is transmitted
again during the next SPI message.
Any bits clocked out of the SO pin after the first sixteen, is
representative of the initial message bits clocked into the SI
pin. That is due to the CS pin first transitioned to a logic [0].
This feature is useful for daisy chaining devices as well as
message verification.
These are
read-only
bits.
ST15:ST8— These bits represent the eight bits from the
RTZ accumulator as determined by the status of bits RZ2 and
RZ3 of the RTZR, defined in Table 8. These bits represent
the integrated signal present on the non-driven coil during an
RTZ event. These bits will be logic[0] after power-on reset, or
after the RST pin transitions from logic [0] to [1]. After an RTZ
event, they will represent the last RTZ accumulator result
before the RTZ was stopped.
ST7—Calibrated clock out of Spec—A logic [1] on this bit
indicates the clock count calibrated to a value outside of the
expected range and given the tolerance specified by T
CLC
in
the
SPI Interface Timing Table.
0 = Clock with in Specification
1 = Clock out of Specification
ST6—Under voltage or over voltage Indication— A logic
[1] on this bit indicates the V
PWR
voltage fell to a level below
the V
PWRUV
, or it exceeded an upper limit of V
PWROV
, as
specified in the
Static Electrical Characteristics Table
, since
the last SPI communication. An under voltage event is just
flagged, while an over voltage event will automatically disable
the driver outputs. Because the pointer may not be in the
expected position, the master may want to re-calibrate the
pointer position with a RTZ command after the voltage
returns to a normal level. For an over voltage event, both
gauges must be re-enabled as soon as this flag returns to
logic [0]. The state machine continues to operate properly as
long as V
DD
is within normal range.
0 = Normal range
1 = Battery voltage fell below V
PWRUV
, or exceeded
V
PWROV
ST5—Gauge 1—Movement since last SPI
communication. A logic [1] on this bit indicates that the Gauge
1 pointer position has changed since the last SPI command.
This allows the master to confirm the pointer is moving as
commanded.
1
1
0
0
49.92
1
1
0
1
54.02
1
1
1
0
58.11
1
1
1
1
62.21
Table 14. RTZCR Accumulator Offset
RC12
RC11
RC10
RC9
RC8
RC7
RC6
RC5
Preload Value (PV)
Initial Accumulator Value = (-16xPV)-1
0
0
0
0
0
0
0
0
0
-1
0
0
0
0
0
0
0
1
1
-17
0
0
0
0
0
0
1
0
2
-33
0
0
0
0
0
0
1
1
3
-49
0
0
0
0
0
1
0
0
4
-65
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
1
1
1
1
1
1
1
1
255
-4081
Table 13. RTZCR Full Step Time
RC3
RC2
RC1
RC0
Full Step Time (ms)
Table 15. Status Output Register
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Read
ST15
ST14
ST13
ST12
ST11
ST10
ST9
ST8
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
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