DETAIL OF CONTROL BITS AND REGISTER MAPPING" />
參數(shù)資料
型號: MCZ33905BD5EK
廠商: Freescale Semiconductor
文件頁數(shù): 71/106頁
文件大小: 0K
描述: IC SBC CAN HS 5.0V 54SOIC
標(biāo)準(zhǔn)包裝: 26
應(yīng)用: 系統(tǒng)基礎(chǔ)芯片
接口: CAN,LIN
電源電壓: 5.5 V ~ 28 V
封裝/外殼: 54-SSOP(0.295",7.50mm 寬)裸露焊盤
供應(yīng)商設(shè)備封裝: 54-SOICW-EP
包裝: 管件
安裝類型: 表面貼裝
Analog Integrated Circuit Device Data
Freescale Semiconductor
67
33903/4/5
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
DETAIL OF CONTROL BITS AND REGISTER MAPPING
The following tables contain register bit meaning arranged by register address, from address 0_000 to address 1_0100
MUX AND RAM REGISTERS
Table 15. MUX Register(39)
MOSI First Byte [15-8]
[b_15 b_14] 0_0000 [P/N]
MOSI Second Byte, bits 7-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 00 _ 000 P
MUX_2
MUX_1
MUX_0
Int 2K
I/O-att
0
Default state
0
Condition for default
POR, 5 V-CAN off, any mode different from Normal
Bits
Description
b7 b6 b5
MUX_2, MUX_1, MUX_0 - Selection of external input signal or internal signal to be measured at MUX-OUT pin
000
All functions disable. No output voltage at MUX-OUT pin
001
VDD regulator current recopy. Ratio is approx 1/97. Requires an external resistor or selection of Internal 2.0 K (bit 3)
010
Device internal voltage reference (approx 2.5 V)
011
Device internal temperature sensor voltage
100
Voltage at I/O-0. Attenuation or gain is selected by bit 3.
101
Voltage at I/O-1. Attenuation or gain is selected by bit 3.
110
Voltage at VSUP/1 pin. Refer to electrical table for attenuation ratio (approx 5)
111
Voltage at VSENSE pin. Refer to electrical table for attenuation ratio (approx 5)
b4
INT 2k - Select device internal 2.0 kohm resistor between AMUX and GND. This resistor allows the measurement of a voltage proportional
to the VDD output current.
0
Internal 2.0 kohm resistor disable. An external resistor must be connected between AMUX and GND.
1
Internal 2.0 kohm resistor enable.
b3
I/O-att - When I/O-0 (or I/O-1) is selected with b7,b6,b5 = 100 (or 101), b3 selects attenuation or gain
between I/O-0 (or I/O-1) and MUX-OUT pin
0
Gain is approx 2 for device with VDD = 5.0 V (Ref. to electrical table for exact gain value)
Gain is approx 1.3 for device with VDD = 3.3 V (Ref. to electrical table for exact gain value)
1
Attenuation is approx 4 for device with VDD = 5.0 V (Ref. to electrical table for exact attenuation value)
Attenuation is approx 6 for device with VDD = 3.3 V (Ref. to electrical table for exact attenuation value)
Notes
39.
The MUX register can be written and read only when the 5V-CAN regulator is ON. If the MUX register is written or read while
5V-CAN is OFF, the command is ignored, and the MXU register content is reset to default state (all control bits = 0).
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